From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOt-0007DL-2C for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOj-0005Xi-TP for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:54 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:48950) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOj-0005Wn-Mu for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:45 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:15:57 +0200 Message-ID: <1399997768-32014-13-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Fabian Aggeler , peter.maydell@linaro.org From: Sergey Fedorov Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index fb72cfa..76c9e90 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -173,6 +173,7 @@ typedef struct CPUARMState { uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ + uint32_t c1_sder; /* Secure debug enable register. */ uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 2c600ef..00dc4af 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2131,6 +2131,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .resetvalue = 0, }, + { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, -- 1.8.3.2