From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOm-0007CS-Mo for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOg-0005WI-Vo for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:48 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOg-0005Vy-QK for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:42 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:15:46 +0200 Message-ID: <1399997768-32014-2-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Svetlana Fedoseeva , Fabian Aggeler , peter.maydell@linaro.org From: Svetlana Fedoseeva Define Security Extensions CPU feature. Set that feature for relevant CPUs. Signed-off-by: Svetlana Fedoseeva Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.c | 4 ++++ target-arm/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index c0ddc3e..b0d4a9b 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -527,6 +527,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_SECURITY_EXTENSIONS); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -613,6 +614,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_SECURITY_EXTENSIONS); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -679,6 +681,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_SECURITY_EXTENSIONS); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -746,6 +749,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_SECURITY_EXTENSIONS); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c83f249..5eba825 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -631,6 +631,7 @@ enum arm_features { ARM_FEATURE_CBAR, /* has cp15 CBAR */ ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ + ARM_FEATURE_SECURITY_EXTENSIONS, /* has Security Extensions */ }; static inline int arm_feature(CPUARMState *env, int feature) -- 1.8.3.2