From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOt-0007DM-3N for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOm-0005Ye-2W for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:54 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24934) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOl-0005Xv-Sw for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:48 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:16:07 +0200 Message-ID: <1399997768-32014-23-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Fabian Aggeler , peter.maydell@linaro.org SCR.{IRQ/FIQ} bits allows to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 2 ++ target-arm/helper.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f6261c2..212cb64 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -673,6 +673,8 @@ static inline int arm_feature(CPUARMState *env, int feature) } #define SCR_NS (1U << 0) +#define SCR_IRQ (1U << 1) +#define SCR_FIQ (1U << 2) /* Return true if the processor is in secure state */ static inline bool arm_is_secure(CPUARMState *env) diff --git a/target-arm/helper.c b/target-arm/helper.c index deff3de..a5ba480 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3597,12 +3597,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.c1_scr & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.c1_scr & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: -- 1.8.3.2