From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOs-0007D8-7W for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOi-0005Wu-C8 for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:54 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOi-0005Vy-5h for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:44 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:15:50 +0200 Message-ID: <1399997768-32014-6-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Svetlana Fedoseeva , Fabian Aggeler , peter.maydell@linaro.org From: Svetlana Fedoseeva Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM state info. Provide CPU mode name for monitor mode. Signed-off-by: Svetlana Fedoseeva Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 7 ++++--- target-arm/helper.c | 2 ++ target-arm/machine.c | 6 +++--- target-arm/translate.c | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5eba825..a56d3d6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -143,9 +143,9 @@ typedef struct CPUARMState { uint32_t spsr; /* Banked registers. */ - uint64_t banked_spsr[6]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint64_t banked_spsr[7]; + uint32_t banked_r13[7]; + uint32_t banked_r14[7]; /* These hold r8-r12. */ uint32_t usr_regs[5]; @@ -563,6 +563,7 @@ enum arm_cpu_mode { ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_SVC = 0x13, + ARM_CPU_MODE_MON = 0x16, ARM_CPU_MODE_ABT = 0x17, ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_SYS = 0x1f diff --git a/target-arm/helper.c b/target-arm/helper.c index 2b57ad9..c1388eb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3095,6 +3095,8 @@ int bank_number(int mode) return 4; case ARM_CPU_MODE_FIQ: return 5; + case ARM_CPU_MODE_MON: + return 6; } hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 810ba27..6c4f7b7 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -238,9 +238,9 @@ const VMStateDescription vmstate_arm_cpu = { .offset = 0, }, VMSTATE_UINT32(env.spsr, ARMCPU), - VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 7), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 7), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 7), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64(env.elr_el1, ARMCPU), diff --git a/target-arm/translate.c b/target-arm/translate.c index a4d920b..46553fa 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11047,7 +11047,7 @@ void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) } static const char *cpu_mode_names[16] = { - "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", + "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", "???", "???", "???", "und", "???", "???", "???", "sys" }; -- 1.8.3.2