From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOt-0007DS-Ld for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOi-0005X4-Me for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:55 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOi-0005Vy-Gn for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:44 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:15:51 +0200 Message-ID: <1399997768-32014-7-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 06/23] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Fabian Aggeler , peter.maydell@linaro.org arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a56d3d6..6ea0432 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -640,6 +640,21 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) { + return ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) || + !(env->cp15.c1_scr & 1); + } else { + return false; + } +#else + return false; +#endif +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { -- 1.8.3.2