From: "Andrew Jeffery" <andrew@aj.id.au>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Joel Stanley <joel@jms.id.au>
Subject: Re: [PATCH 03/21] hw: aspeed_scu: Add AST2600 support
Date: Fri, 20 Sep 2019 13:40:58 +0930 [thread overview]
Message-ID: <139c3f7e-465e-4efb-b6c7-213dcd2ec6b7@www.fastmail.com> (raw)
In-Reply-To: <20190919055002.6729-4-clg@kaod.org>
On Thu, 19 Sep 2019, at 15:19, Cédric Le Goater wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> The SCU controller on the AST2600 SoC has extra registers. Increase
> the number of regs of the model and introduce a new field in the class
> to customize the MemoryRegion operations depending on the SoC model.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> [clg: - improved commit log
> - changed vmstate version
> - reworked model integration into new objet class ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/misc/aspeed_scu.h | 7 +-
> hw/misc/aspeed_scu.c | 190 +++++++++++++++++++++++++++++++++--
> 2 files changed, 189 insertions(+), 8 deletions(-)
...
> +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
> uint64_t data,
> + unsigned size)
> +{
> + AspeedSCUState *s = ASPEED_SCU(opaque);
> + int reg = TO_REG(offset);
> +
> + if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Out-of-bounds write at offset 0x%"
> HWADDR_PRIx "\n",
> + __func__, offset);
> + return;
> + }
> +
> + if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n",
> __func__);
> + }
> +
> + trace_aspeed_scu_write(offset, size, data);
> +
> + switch (reg) {
> + case AST2600_PROT_KEY:
> + s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
> + return;
> + case AST2600_HW_STRAP1:
> + case AST2600_HW_STRAP2:
> + if (s->regs[reg + 2]) {
> + return;
> + }
> + /* fall through */
> + case AST2600_SYS_RST_CTRL:
> + case AST2600_SYS_RST_CTRL2:
> + /* W1S (Write 1 to set) registers */
> + s->regs[reg] |= data;
> + return;
> + case AST2600_SYS_RST_CTRL_CLR:
> + case AST2600_SYS_RST_CTRL2_CLR:
> + case AST2600_HW_STRAP1_CLR:
> + case AST2600_HW_STRAP2_CLR:
> + /* W1C (Write 1 to clear) registers */
> + s->regs[reg] &= ~data;
This clear should respect the protection register for each strap case.
Andrew
next prev parent reply other threads:[~2019-09-20 4:26 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-19 5:49 [Qemu-devel] [PATCH 00/21] aspeed: Add support for the AST2600 SoC Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 01/21] aspeed/wdt: Check correct register for clock source Cédric Le Goater
2019-09-20 4:41 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 02/21] hw/sd/aspeed_sdhci: New device Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 03/21] hw: aspeed_scu: Add AST2600 support Cédric Le Goater
2019-09-20 4:10 ` Andrew Jeffery [this message]
2019-09-20 15:15 ` Cédric Le Goater
2019-09-21 4:37 ` Joel Stanley
2019-09-23 5:44 ` Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 04/21] aspeed/timer: Introduce an object class per SoC Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 05/21] aspeed/timer: Add support for control register 3 Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 06/21] aspeed/timer: Add AST2600 support Cédric Le Goater
2019-09-20 4:42 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600 Cédric Le Goater
2019-09-20 4:43 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 08/21] aspeed/sdmc: Introduce an object class per SoC Cédric Le Goater
2019-09-20 4:51 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 09/21] aspeed/sdmc: Add AST2600 support Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 10/21] watchdog/aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-20 4:44 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 11/21] hw: wdt_aspeed: Add AST2600 support Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 12/21] aspeed/smc: " Cédric Le Goater
2019-09-20 4:46 ` Joel Stanley
2019-09-20 15:24 ` Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 13/21] hw/gpio: Add in AST2600 specific implementation Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 14/21] aspeed/i2c: Introduce an object class per SoC Cédric Le Goater
2019-09-20 4:47 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 15/21] aspeed/i2c: Add AST2600 support Cédric Le Goater
2019-09-20 4:48 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 16/21] aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-20 4:49 ` Joel Stanley
2019-09-19 5:49 ` [Qemu-devel] [PATCH 17/21] aspeed/soc: Add AST2600 support Cédric Le Goater
2019-09-20 4:35 ` Joel Stanley
2019-09-20 15:17 ` Cédric Le Goater
2019-09-19 5:49 ` [Qemu-devel] [PATCH 18/21] aspeed: Add an AST2600 eval board Cédric Le Goater
2019-09-20 4:40 ` Joel Stanley
2019-09-19 5:50 ` [Qemu-devel] [PATCH 19/21] aspeed: Parameterise number of MACs Cédric Le Goater
2019-09-19 5:50 ` [Qemu-devel] [PATCH 20/21] aspeed: add support for the Aspeed MII controller of the AST2600 Cédric Le Goater
2019-09-20 4:50 ` Joel Stanley
2019-09-19 5:50 ` [Qemu-devel] [PATCH 21/21] aspeed/soc: Add ASPEED Video stub Cédric Le Goater
2019-09-19 20:56 ` [Qemu-devel] [PATCH 00/21] aspeed: Add support for the AST2600 SoC no-reply
2019-09-20 3:34 ` Andrew Jeffery
2019-09-20 6:19 ` Cédric Le Goater
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