From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 2/2] target/arm: Use tcg_gen_gvec_bitsel
Date: Thu, 23 May 2019 09:16:21 -0400 [thread overview]
Message-ID: <13d9e22b-4ac5-fb87-622c-a99b5494d06c@linaro.org> (raw)
In-Reply-To: <CAFEAcA_1XuWqVu9gonn5_Y9x1V=UcWNHEXtwop2s0qyUbwiZpg@mail.gmail.com>
On 5/23/19 9:08 AM, Peter Maydell wrote:
>> Because the three different instructions perform the same operation with
>> reshuffled register arguments.
>
> Ah, so they do. Next question, how do I find out what the
> order of arguments in the above code means so I can compare
> it against the pseudocode expression we're implementing?
>From tcg/README:
* bitsel_vec v0, v1, v2, v3
Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
The "selector" is second, the first input operand.
r~
next prev parent reply other threads:[~2019-05-23 13:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-18 19:19 [Qemu-devel] [PATCH 0/2] target/arm: make use of new gvec expanders Richard Henderson
2019-05-18 19:19 ` [Qemu-devel] [PATCH 1/2] target/arm: Vectorize USHL and SSHL Richard Henderson
2019-05-23 12:44 ` Peter Maydell
2019-05-23 13:03 ` Peter Maydell
2019-06-03 17:23 ` Richard Henderson
2019-05-18 19:19 ` [Qemu-devel] [PATCH 2/2] target/arm: Use tcg_gen_gvec_bitsel Richard Henderson
2019-05-23 12:46 ` Peter Maydell
2019-05-23 13:02 ` Richard Henderson
2019-05-23 13:08 ` Peter Maydell
2019-05-23 13:16 ` Richard Henderson [this message]
2019-05-23 13:30 ` Peter Maydell
2019-06-03 18:15 ` Richard Henderson
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