From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmK0S-00076Y-6E for qemu-devel@nongnu.org; Mon, 19 May 2014 05:37:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmK0M-0001T1-7Y for qemu-devel@nongnu.org; Mon, 19 May 2014 05:37:16 -0400 Received: from mail-we0-x230.google.com ([2a00:1450:400c:c03::230]:62070) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmK0M-0001Sx-23 for qemu-devel@nongnu.org; Mon, 19 May 2014 05:37:10 -0400 Received: by mail-we0-f176.google.com with SMTP id q59so5256116wes.35 for ; Mon, 19 May 2014 02:37:09 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 19 May 2014 19:23:01 +1000 Message-Id: <1400491383-6725-21-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400491383-6725-1-git-send-email-edgar.iglesias@gmail.com> References: <1400491383-6725-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v3 20/22] target-arm: A64: Register VBAR_EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/helper.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 693ad0f..566f9ed 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -198,7 +198,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[3]; /* vector base address register */ + uint64_t vbar_el[4]; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 7ca63a8..9bc5b3d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2114,6 +2114,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, + .access = PL3_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), + .resetvalue = 0 }, REGINFO_SENTINEL }; -- 1.8.3.2