From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
Tom Musta <tommusta@gmail.com>,
qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs
Date: Wed, 21 May 2014 16:20:22 +1000 [thread overview]
Message-ID: <1400653228-31540-4-git-send-email-aik@ozlabs.ru> (raw)
In-Reply-To: <1400653228-31540-1-git-send-email-aik@ozlabs.ru>
This adds TIR/SIAR/SDAR/MMCRA/MMCR0/MMCR1.
This redefines UMMCRA (was MCCRA) and defines hypv version of if.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 10 +++++++++-
target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++----
2 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 13eea19..262cf0f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1371,6 +1371,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_GIVOR8 (0x1BB)
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
+#define SPR_TIR (0x1BE)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
@@ -1463,7 +1464,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
-#define SPR_MMCRA (0x302)
+#define SPR_UMMCRA (0x302)
#define SPR_PERF3 (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
@@ -1485,17 +1486,22 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERFB (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
+#define SPR_POWER_UMMCR0 (0x30B)
#define SPR_PERFC (0x30C)
#define SPR_MPC_MD_TWB (0x30C)
+#define SPR_BOOK3S_SIAR (0x30C)
+#define SPR_BOOK3S_SDAR (0x30D)
#define SPR_PERFD (0x30D)
#define SPR_MPC_MD_TWC (0x30D)
#define SPR_PERFE (0x30E)
#define SPR_MPC_MD_RPN (0x30E)
+#define SPR_POWER_UMMCR1 (0x30E)
#define SPR_PERFF (0x30F)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
+#define SPR_MMCRA (0x312)
#define SPR_UPERF3 (0x313)
#define SPR_UPERF4 (0x314)
#define SPR_UPERF5 (0x315)
@@ -1505,9 +1511,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERF9 (0x319)
#define SPR_UPERFA (0x31A)
#define SPR_UPERFB (0x31B)
+#define SPR_POWER_MMCR0 (0x31B)
#define SPR_UPERFC (0x31C)
#define SPR_UPERFD (0x31D)
#define SPR_UPERFE (0x31E)
+#define SPR_POWER_MMCR1 (0x31E)
#define SPR_UPERFF (0x31F)
#define SPR_RCPU_MI_RA0 (0x320)
#define SPR_MPC_MI_DBCAM (0x320)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e9c37fa..b92b447 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7687,6 +7687,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
+
+ spr_register(env, SPR_TIR, "TIR",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
}
static void gen_spr_book3s_purr(CPUPPCState *env)
@@ -7711,16 +7716,20 @@ static void gen_spr_book3s_debug(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
+ spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIAR, 0x00000000);
+ spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SDAR, 0x00000000);
#endif
}
static void gen_spr_book3s_pmu(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRA, 0x00000000);
spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -7729,6 +7738,30 @@ static void gen_spr_book3s_pmu(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
+ spr_register(env, SPR_MMCRA, "MMCRA",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_UMMCRA, "UMMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register(env, SPR_POWER_MMCR0, "MMCR0",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_UMMCR0, "UMMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR0, 0x00000000);
+ spr_register(env, SPR_POWER_MMCR1, "MMCR1",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_UMMCR1, "UMMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR1, 0x00000000);
#endif
}
--
1.9.rc0
next prev parent reply other threads:[~2014-05-21 6:21 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants Alexey Kardashevskiy
2014-05-21 16:55 ` Tom Musta
2014-05-22 2:53 ` Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7 Alexey Kardashevskiy
2014-05-21 10:44 ` Alexander Graf
2014-05-21 12:30 ` Alexey Kardashevskiy
2014-05-21 13:23 ` Alexander Graf
2014-05-22 3:59 ` Alexey Kardashevskiy
2014-05-22 7:08 ` Alexander Graf
2014-05-21 6:20 ` Alexey Kardashevskiy [this message]
2014-05-21 17:17 ` [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8 Alexey Kardashevskiy
2014-05-21 17:22 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs Alexey Kardashevskiy
2014-05-21 10:47 ` Alexander Graf
2014-05-21 18:08 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-05-21 10:53 ` Alexander Graf
2014-05-21 6:20 ` [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration Alexey Kardashevskiy
2014-05-21 18:11 ` Tom Musta
2014-05-22 2:50 ` Alexey Kardashevskiy
2014-05-22 11:39 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 8/9] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-05-21 11:44 ` Alexander Graf
2014-05-21 12:24 ` Alexey Kardashevskiy
2014-05-21 12:25 ` Alexander Graf
2014-05-21 12:26 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
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