* [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 16:55 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7 Alexey Kardashevskiy
` (7 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
MMCR0 and MMCR1 have different numbers for 32 and 64 bit POWERPC.
We are going to support 64bit versions too so let's rename 32bit ones
to avoid confusion.
604 uses same SPR number for MMCR0 so it is included in this patch too.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 8 ++++----
target-ppc/translate_init.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b035e91..13eea19 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1567,11 +1567,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPMC5 (0x3A1)
#define SPR_UPMC6 (0x3A2)
#define SPR_UBAMR (0x3A7)
-#define SPR_UMMCR0 (0x3A8)
+#define SPR_7XX_UMMCR0 (0x3A8)
#define SPR_UPMC1 (0x3A9)
#define SPR_UPMC2 (0x3AA)
#define SPR_USIAR (0x3AB)
-#define SPR_UMMCR1 (0x3AC)
+#define SPR_7XX_UMMCR1 (0x3AC)
#define SPR_UPMC3 (0x3AD)
#define SPR_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
@@ -1590,14 +1590,14 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_405_DVC1 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
#define SPR_BAMR (0x3B7)
-#define SPR_MMCR0 (0x3B8)
+#define SPR_7XX_MMCR0 (0x3B8)
#define SPR_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
#define SPR_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
#define SPR_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
-#define SPR_MMCR1 (0x3BC)
+#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
#define SPR_PMC3 (0x3BD)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 16ecada..bf5ea09 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -951,12 +951,12 @@ static void gen_spr_7xx (CPUPPCState *env)
0x00000000);
/* Performance monitors */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -986,12 +986,12 @@ static void gen_spr_7xx (CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR0, "UMMCR0",
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR1, "UMMCR1",
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -1117,7 +1117,7 @@ static void gen_spr_604 (CPUPPCState *env)
KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -5436,7 +5436,7 @@ static void init_proc_604E (CPUPPCState *env)
gen_spr_ne_601(env);
gen_spr_604(env);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants
2014-05-21 6:20 ` [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants Alexey Kardashevskiy
@ 2014-05-21 16:55 ` Tom Musta
2014-05-22 2:53 ` Alexey Kardashevskiy
0 siblings, 1 reply; 29+ messages in thread
From: Tom Musta @ 2014-05-21 16:55 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
> MMCR0 and MMCR1 have different numbers for 32 and 64 bit POWERPC.
> We are going to support 64bit versions too so let's rename 32bit ones
> to avoid confusion.
>
> 604 uses same SPR number for MMCR0 so it is included in this patch too.
I'm not sure that it is a 32-bit vs. 64-bit thing as much as it is an
evolution of Performance Monitor from individual Book IVs into the
ISA. Saying differently, the SPR number for MMCR0 is now specified
in the ISA and is the same for 32 and 64 bit implementations
... and is also the same for embedded versus server implementations.
When the 604 came out, the performance monitor was not yet part of
the ISA.
Other than that ...
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants
2014-05-21 16:55 ` Tom Musta
@ 2014-05-22 2:53 ` Alexey Kardashevskiy
0 siblings, 0 replies; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-22 2:53 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 05/22/2014 02:55 AM, Tom Musta wrote:
> On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
>> MMCR0 and MMCR1 have different numbers for 32 and 64 bit POWERPC.
>> We are going to support 64bit versions too so let's rename 32bit ones
>> to avoid confusion.
>>
>> 604 uses same SPR number for MMCR0 so it is included in this patch too.
>
> I'm not sure that it is a 32-bit vs. 64-bit thing as much as it is an
> evolution of Performance Monitor from individual Book IVs into the
> ISA. Saying differently, the SPR number for MMCR0 is now specified
> in the ISA and is the same for 32 and 64 bit implementations
> ... and is also the same for embedded versus server implementations.
> When the 604 came out, the performance monitor was not yet part of
> the ISA.
The kernel has 2 definitions for MMCR0 and 32 vs. 64 is the condition to
choose one or the other. This is not a spec but still something :)
> Other than that ...
>
> Reviewed-by: Tom Musta <tommusta@gmail.com>
>
--
Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 10:44 ` Alexander Graf
2014-05-21 6:20 ` [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs Alexey Kardashevskiy
` (6 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves SPR initialization to helper functions.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 83 +++++++++++++++++++++++++++++++++------------
1 file changed, 62 insertions(+), 21 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bf5ea09..e9c37fa 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7680,17 +7680,17 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x10000;
}
-static void init_proc_POWER7 (CPUPPCState *env)
+static void gen_spr_book3s_ids(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
+}
+
+static void gen_spr_book3s_purr(CPUPPCState *env)
+{
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
spr_register_kvm(env, SPR_PURR, "PURR",
@@ -7701,14 +7701,22 @@ static void init_proc_POWER7 (CPUPPCState *env)
&spr_read_purr, SPR_NOACCESS,
&spr_read_purr, SPR_NOACCESS,
KVM_REG_PPC_SPURR, 0x00000000);
+#endif
+}
+
+static void gen_spr_book3s_debug(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_CFAR, "SPR_CFAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSCR, 0x00000000);
+#endif
+}
+
+static void gen_spr_book3s_pmu(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -7721,8 +7729,34 @@ static void init_proc_POWER7 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
-#endif /* !CONFIG_USER_ONLY */
- gen_spr_amr(env);
+#endif
+}
+
+static void gen_spr_book3s_vr(CPUPPCState *env)
+{
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_lpar(CPUPPCState *env)
+{
+ /* Logical partitionning */
+ spr_register_kvm(env, SPR_LPCR, "LPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_LPCR, 0x00000000);
+}
+
+static void gen_spr_book3s_common(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSCR, 0x00000000);
+#endif
/* XXX : not implemented */
spr_register(env, SPR_CTRL, "SPR_CTRLT",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7732,22 +7766,29 @@ static void init_proc_POWER7 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x80800000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_PPR, "PPR",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
+}
+
+static void init_proc_POWER7 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_book3s_ids(env);
+ gen_spr_book3s_common(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_vr(env);
+ gen_spr_book3s_lpar(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_book3s_debug(env);
+ gen_spr_book3s_pmu(env);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
-#endif
+#endif /* !CONFIG_USER_ONLY */
init_excp_POWER7(env);
env->dcache_line_size = 128;
env->icache_line_size = 128;
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-21 6:20 ` [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7 Alexey Kardashevskiy
@ 2014-05-21 10:44 ` Alexander Graf
2014-05-21 12:30 ` Alexey Kardashevskiy
0 siblings, 1 reply; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 10:44 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 08:20, Alexey Kardashevskiy wrote:
> This moves SPR initialization to helper functions.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
I like the idea, but please refactor all book3s CPUs, not just POWER7.
I also think we can cover a lot of the SPR registration by matching on
feature fields. VR for example is coupled to Altivec.
Maybe we could also introduce an enum for the exact cpu type, similar to
how we do it on e500? Then we could do fun things like
if (cpu_type >= CPU_TYPE_970) {
gen_spr_book3s_vr(env);
}
if (cpu_type >= CPU_TYPE_POWER7) {
gen_spr_lpar(env);
}
switch (cpu_type) {
case CPU_TYPE_POWER7:
env->slb_nr = 32;
break;
default:
env->slb_nr = 64;
break;
}
and thus combine all those book3s init functions into a single, more
maintainable version.
Alex
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-21 10:44 ` Alexander Graf
@ 2014-05-21 12:30 ` Alexey Kardashevskiy
2014-05-21 13:23 ` Alexander Graf
0 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 12:30 UTC (permalink / raw)
To: Alexander Graf, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 05/21/2014 08:44 PM, Alexander Graf wrote:
>
> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>> This moves SPR initialization to helper functions.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> I like the idea, but please refactor all book3s CPUs, not just POWER7.
>
> I also think we can cover a lot of the SPR registration by matching on
> feature fields. VR for example is coupled to Altivec.
Ok.
> Maybe we could also introduce an enum for the exact cpu type, similar to
> how we do it on e500? Then we could do fun things like
>
> if (cpu_type >= CPU_TYPE_970) {
> gen_spr_book3s_vr(env);
> }
>
> if (cpu_type >= CPU_TYPE_POWER7) {
> gen_spr_lpar(env);
> }
>
> switch (cpu_type) {
> case CPU_TYPE_POWER7:
> env->slb_nr = 32;
> break;
> default:
> env->slb_nr = 64;
> break;
> }
>
> and thus combine all those book3s init functions into a single, more
> maintainable version.
If I can, I would like not to do it in this way, I'd rather have explicit
list of gen_spr_FACILITY() calls always. For example,
DABR/DABRX/whateverPOWER8has - it is not going to be always ">", and this
breaks my weak mind :(
--
Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-21 12:30 ` Alexey Kardashevskiy
@ 2014-05-21 13:23 ` Alexander Graf
2014-05-22 3:59 ` Alexey Kardashevskiy
0 siblings, 1 reply; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 13:23 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 14:30, Alexey Kardashevskiy wrote:
> On 05/21/2014 08:44 PM, Alexander Graf wrote:
>> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>>> This moves SPR initialization to helper functions.
>>>
>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> I like the idea, but please refactor all book3s CPUs, not just POWER7.
>>
>> I also think we can cover a lot of the SPR registration by matching on
>> feature fields. VR for example is coupled to Altivec.
>
> Ok.
>
>> Maybe we could also introduce an enum for the exact cpu type, similar to
>> how we do it on e500? Then we could do fun things like
>>
>> if (cpu_type >= CPU_TYPE_970) {
>> gen_spr_book3s_vr(env);
>> }
>>
>> if (cpu_type >= CPU_TYPE_POWER7) {
>> gen_spr_lpar(env);
>> }
>>
>> switch (cpu_type) {
>> case CPU_TYPE_POWER7:
>> env->slb_nr = 32;
>> break;
>> default:
>> env->slb_nr = 64;
>> break;
>> }
>>
>> and thus combine all those book3s init functions into a single, more
>> maintainable version.
> If I can, I would like not to do it in this way, I'd rather have explicit
> list of gen_spr_FACILITY() calls always. For example,
> DABR/DABRX/whateverPOWER8has - it is not going to be always ">", and this
> breaks my weak mind :(
Could you give me some examples where a newer POWER has lost features
over an older POWER?
Alex
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-21 13:23 ` Alexander Graf
@ 2014-05-22 3:59 ` Alexey Kardashevskiy
2014-05-22 7:08 ` Alexander Graf
0 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-22 3:59 UTC (permalink / raw)
To: Alexander Graf, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 05/21/2014 11:23 PM, Alexander Graf wrote:
>
> On 21.05.14 14:30, Alexey Kardashevskiy wrote:
>> On 05/21/2014 08:44 PM, Alexander Graf wrote:
>>> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>>>> This moves SPR initialization to helper functions.
>>>>
>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>> I like the idea, but please refactor all book3s CPUs, not just POWER7.
>>>
>>> I also think we can cover a lot of the SPR registration by matching on
>>> feature fields. VR for example is coupled to Altivec.
>>
>> Ok.
>>
>>> Maybe we could also introduce an enum for the exact cpu type, similar to
>>> how we do it on e500? Then we could do fun things like
>>>
>>> if (cpu_type >= CPU_TYPE_970) {
>>> gen_spr_book3s_vr(env);
>>> }
>>>
>>> if (cpu_type >= CPU_TYPE_POWER7) {
>>> gen_spr_lpar(env);
>>> }
>>>
>>> switch (cpu_type) {
>>> case CPU_TYPE_POWER7:
>>> env->slb_nr = 32;
>>> break;
>>> default:
>>> env->slb_nr = 64;
>>> break;
>>> }
>>>
>>> and thus combine all those book3s init functions into a single, more
>>> maintainable version.
>> If I can, I would like not to do it in this way, I'd rather have explicit
>> list of gen_spr_FACILITY() calls always. For example,
>> DABR/DABRX/whateverPOWER8has - it is not going to be always ">", and this
>> breaks my weak mind :(
>
> Could you give me some examples where a newer POWER has lost features over
> an older POWER?
DABR/DABRX, also Paul mentioned "one exception is the instructions in
power6 that are register moves between gpr and fpr registers". I do not
know anything else though. So your point is taken, I'll try to do what you
want :)
--
Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7
2014-05-22 3:59 ` Alexey Kardashevskiy
@ 2014-05-22 7:08 ` Alexander Graf
0 siblings, 0 replies; 29+ messages in thread
From: Alexander Graf @ 2014-05-22 7:08 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: Tom Musta, qemu-ppc@nongnu.org, qemu-devel@nongnu.org
> Am 22.05.2014 um 05:59 schrieb Alexey Kardashevskiy <aik@ozlabs.ru>:
>
>> On 05/21/2014 11:23 PM, Alexander Graf wrote:
>>
>>> On 21.05.14 14:30, Alexey Kardashevskiy wrote:
>>>> On 05/21/2014 08:44 PM, Alexander Graf wrote:
>>>>> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>>>>> This moves SPR initialization to helper functions.
>>>>>
>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>> I like the idea, but please refactor all book3s CPUs, not just POWER7.
>>>>
>>>> I also think we can cover a lot of the SPR registration by matching on
>>>> feature fields. VR for example is coupled to Altivec.
>>>
>>> Ok.
>>>
>>>> Maybe we could also introduce an enum for the exact cpu type, similar to
>>>> how we do it on e500? Then we could do fun things like
>>>>
>>>> if (cpu_type >= CPU_TYPE_970) {
>>>> gen_spr_book3s_vr(env);
>>>> }
>>>>
>>>> if (cpu_type >= CPU_TYPE_POWER7) {
>>>> gen_spr_lpar(env);
>>>> }
>>>>
>>>> switch (cpu_type) {
>>>> case CPU_TYPE_POWER7:
>>>> env->slb_nr = 32;
>>>> break;
>>>> default:
>>>> env->slb_nr = 64;
>>>> break;
>>>> }
>>>>
>>>> and thus combine all those book3s init functions into a single, more
>>>> maintainable version.
>>> If I can, I would like not to do it in this way, I'd rather have explicit
>>> list of gen_spr_FACILITY() calls always. For example,
>>> DABR/DABRX/whateverPOWER8has - it is not going to be always ">", and this
>>> breaks my weak mind :(
>>
>> Could you give me some examples where a newer POWER has lost features over
>> an older POWER?
>
> DABR/DABRX, also Paul mentioned "one exception is the instructions in
> power6 that are register moves between gpr and fpr registers".
For those cases, just switch() explicitly for the cpu type. We don't have to arithmetically solve all of the feature matches :)
Alex
> I do not
> know anything else though. So your point is taken, I'll try to do what you
> want :)
>
>
> --
> Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 1/9] target-ppc: Rename MMCR0/1 contants Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 2/9] target-ppc: Refactor init_proc_POWER7 Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 17:17 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8 Alexey Kardashevskiy
` (5 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds TIR/SIAR/SDAR/MMCRA/MMCR0/MMCR1.
This redefines UMMCRA (was MCCRA) and defines hypv version of if.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 10 +++++++++-
target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++----
2 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 13eea19..262cf0f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1371,6 +1371,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_GIVOR8 (0x1BB)
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
+#define SPR_TIR (0x1BE)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
@@ -1463,7 +1464,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
-#define SPR_MMCRA (0x302)
+#define SPR_UMMCRA (0x302)
#define SPR_PERF3 (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
@@ -1485,17 +1486,22 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERFB (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
+#define SPR_POWER_UMMCR0 (0x30B)
#define SPR_PERFC (0x30C)
#define SPR_MPC_MD_TWB (0x30C)
+#define SPR_BOOK3S_SIAR (0x30C)
+#define SPR_BOOK3S_SDAR (0x30D)
#define SPR_PERFD (0x30D)
#define SPR_MPC_MD_TWC (0x30D)
#define SPR_PERFE (0x30E)
#define SPR_MPC_MD_RPN (0x30E)
+#define SPR_POWER_UMMCR1 (0x30E)
#define SPR_PERFF (0x30F)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
+#define SPR_MMCRA (0x312)
#define SPR_UPERF3 (0x313)
#define SPR_UPERF4 (0x314)
#define SPR_UPERF5 (0x315)
@@ -1505,9 +1511,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERF9 (0x319)
#define SPR_UPERFA (0x31A)
#define SPR_UPERFB (0x31B)
+#define SPR_POWER_MMCR0 (0x31B)
#define SPR_UPERFC (0x31C)
#define SPR_UPERFD (0x31D)
#define SPR_UPERFE (0x31E)
+#define SPR_POWER_MMCR1 (0x31E)
#define SPR_UPERFF (0x31F)
#define SPR_RCPU_MI_RA0 (0x320)
#define SPR_MPC_MI_DBCAM (0x320)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e9c37fa..b92b447 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7687,6 +7687,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
+
+ spr_register(env, SPR_TIR, "TIR",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
}
static void gen_spr_book3s_purr(CPUPPCState *env)
@@ -7711,16 +7716,20 @@ static void gen_spr_book3s_debug(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
+ spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIAR, 0x00000000);
+ spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SDAR, 0x00000000);
#endif
}
static void gen_spr_book3s_pmu(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRA, 0x00000000);
spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -7729,6 +7738,30 @@ static void gen_spr_book3s_pmu(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
+ spr_register(env, SPR_MMCRA, "MMCRA",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_UMMCRA, "UMMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register(env, SPR_POWER_MMCR0, "MMCR0",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_UMMCR0, "UMMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR0, 0x00000000);
+ spr_register(env, SPR_POWER_MMCR1, "MMCR1",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_UMMCR1, "UMMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR1, 0x00000000);
#endif
}
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs
2014-05-21 6:20 ` [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs Alexey Kardashevskiy
@ 2014-05-21 17:17 ` Tom Musta
0 siblings, 0 replies; 29+ messages in thread
From: Tom Musta @ 2014-05-21 17:17 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
> This adds TIR/SIAR/SDAR/MMCRA/MMCR0/MMCR1.
>
> This redefines UMMCRA (was MCCRA) and defines hypv version of if.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 10 +++++++++-
> target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++----
> 2 files changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 13eea19..262cf0f 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
[...]
> @@ -1505,9 +1511,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_UPERF9 (0x319)
> #define SPR_UPERFA (0x31A)
> #define SPR_UPERFB (0x31B)
> +#define SPR_POWER_MMCR0 (0x31B)
> #define SPR_UPERFC (0x31C)
> #define SPR_UPERFD (0x31D)
> #define SPR_UPERFE (0x31E)
> +#define SPR_POWER_MMCR1 (0x31E)
> #define SPR_UPERFF (0x31F)
Since MMCR0 and MMCR1 SPRs are assigned by the ISA, why "SPR_POWER_MMCR0" instead of just
"SPR_MMCR0" (ditto for MMCR1)? Since you moved the outdated and unoffical 7xx encodings
out of the way in patch 1, the extra "_POWER" seems extraneous.
> #define SPR_RCPU_MI_RA0 (0x320)
> #define SPR_MPC_MI_DBCAM (0x320)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e9c37fa..b92b447 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
[ ... ]
> static void gen_spr_book3s_purr(CPUPPCState *env)
> @@ -7711,16 +7716,20 @@ static void gen_spr_book3s_debug(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_cfar, &spr_write_cfar,
> 0x00000000);
> + spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_SIAR, 0x00000000);
> + spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_SDAR, 0x00000000);
> #endif
> }
SIAR and SDAR are read-only SPRs.
>
> static void gen_spr_book3s_pmu(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> - spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_MMCRA, 0x00000000);
> spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -7729,6 +7738,30 @@ static void gen_spr_book3s_pmu(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_PMC6, 0x00000000);
> + spr_register(env, SPR_MMCRA, "MMCRA",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register_kvm(env, SPR_UMMCRA, "UMMCRA",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCRA, 0x00000000);
> + spr_register(env, SPR_POWER_MMCR0, "MMCR0",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register_kvm(env, SPR_POWER_UMMCR0, "UMMCR0",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCR0, 0x00000000);
> + spr_register(env, SPR_POWER_MMCR1, "MMCR1",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register_kvm(env, SPR_POWER_UMMCR1, "UMMCR1",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCR1, 0x00000000);
> #endif
> }
>
>
This looks wrong to me .... the Uxxxx SPR numbers are accessible in user space (they are Book I
SPRs) whereas the non-Uxxxx forms are not accessible from user space.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (2 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 17:22 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs Alexey Kardashevskiy
` (4 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This duplicates code of init_proc_POWER7() in init_proc_POWER8() as
there will be registers implemented in POWER7 and missing in POWER8
so we need separate init functions for POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b92b447..3c37e93 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7953,10 +7953,31 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
static void init_proc_POWER8(CPUPPCState *env)
{
- /* inherit P7 */
- init_proc_POWER7(env);
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_book3s_ids(env);
+ gen_spr_book3s_common(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_vr(env);
+ gen_spr_book3s_lpar(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_book3s_debug(env);
+ gen_spr_book3s_pmu(env);
+#if !defined(CONFIG_USER_ONLY)
+ env->slb_nr = 32;
+#endif /* !CONFIG_USER_ONLY */
+ init_excp_POWER7(env);
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ ppcPOWER7_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
- /* P8 supports the TAR */
spr_register(env, SPR_TAR, "TAR",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8
2014-05-21 6:20 ` [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8 Alexey Kardashevskiy
@ 2014-05-21 17:22 ` Tom Musta
0 siblings, 0 replies; 29+ messages in thread
From: Tom Musta @ 2014-05-21 17:22 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
> This duplicates code of init_proc_POWER7() in init_proc_POWER8() as
> there will be registers implemented in POWER7 and missing in POWER8
> so we need separate init functions for POWER7 and POWER8.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 27 ++++++++++++++++++++++++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b92b447..3c37e93 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7953,10 +7953,31 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
>
> static void init_proc_POWER8(CPUPPCState *env)
> {
> - /* inherit P7 */
> - init_proc_POWER7(env);
> + gen_spr_ne_601(env);
> + gen_spr_7xx(env);
> + /* Time base */
> + gen_tbl(env);
> + gen_spr_book3s_ids(env);
> + gen_spr_book3s_common(env);
> + gen_spr_amr(env);
> + gen_spr_book3s_vr(env);
> + gen_spr_book3s_lpar(env);
> + gen_spr_book3s_purr(env);
> + gen_spr_book3s_debug(env);
> + gen_spr_book3s_pmu(env);
> +#if !defined(CONFIG_USER_ONLY)
> + env->slb_nr = 32;
> +#endif /* !CONFIG_USER_ONLY */
> + init_excp_POWER7(env);
> + env->dcache_line_size = 128;
> + env->icache_line_size = 128;
> +
> + /* Allocate hardware IRQ controller */
> + ppcPOWER7_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
>
> - /* P8 supports the TAR */
> spr_register(env, SPR_TAR, "TAR",
> &spr_read_generic, &spr_write_generic,
> &spr_read_generic, &spr_write_generic,
>
Now that you have refactored the old MMCRx and new MMCRx SPR numbering, it looks like both old and new
are assigned in the P7 and P8 models. Saying differently, you are calling gen_spr_7xx for P7/P7 and
that routine assigns the old MMCRx SPRs.
Intentional?
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (3 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 4/9] target-ppc: Refactor init_proc_POWER8 Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 10:47 ` Alexander Graf
2014-05-21 18:08 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
` (3 subsequent siblings)
8 siblings, 2 replies; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/
EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs.
This adds MMCR2/FSCR/MMCRS SPRs.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 15 ++++++
target-ppc/translate_init.c | 123 ++++++++++++++++++++++++++++++++++----------
2 files changed, 112 insertions(+), 26 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 262cf0f..72ed763 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_EIE (0x050)
#define SPR_MPC_EID (0x051)
#define SPR_MPC_NRI (0x052)
+#define SPR_TFHAR (0x080)
+#define SPR_TFIAR (0x081)
+#define SPR_TEXASR (0x082)
+#define SPR_TEXASRU (0x083)
#define SPR_UCTRL (0x088)
#define SPR_MPC_CMPA (0x090)
#define SPR_MPC_CMPB (0x091)
@@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_CTRL (0x098)
#define SPR_MPC_CMPE (0x098)
#define SPR_MPC_CMPF (0x099)
+#define SPR_FSCR (0x099)
#define SPR_MPC_CMPG (0x09A)
#define SPR_MPC_CMPH (0x09B)
#define SPR_MPC_LCTRL1 (0x09C)
@@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MI_CTR (0x300)
#define SPR_PERF1 (0x301)
#define SPR_RCPU_MI_RBA1 (0x301)
+#define SPR_POWER_UMMCR2 (0x301)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
@@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
+#define SPR_POWER_MMCR2 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_MMCRA (0x312)
#define SPR_UPERF3 (0x313)
@@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERFF (0x31F)
#define SPR_RCPU_MI_RA0 (0x320)
#define SPR_MPC_MI_DBCAM (0x320)
+#define SPR_BESCRS (0x320)
#define SPR_RCPU_MI_RA1 (0x321)
#define SPR_MPC_MI_DBRAM0 (0x321)
+#define SPR_BESCRSU (0x321)
#define SPR_RCPU_MI_RA2 (0x322)
#define SPR_MPC_MI_DBRAM1 (0x322)
+#define SPR_BESCRR (0x322)
#define SPR_RCPU_MI_RA3 (0x323)
+#define SPR_BESCRRU (0x323)
+#define SPR_EBBHR (0x324)
+#define SPR_EBBRR (0x325)
+#define SPR_BESCR (0x326)
#define SPR_RCPU_L2U_RA0 (0x328)
#define SPR_MPC_MD_DBCAM (0x328)
#define SPR_RCPU_L2U_RA1 (0x329)
@@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_440_ITV3 (0x377)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
+#define SPR_MMCRS (0x37E)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3c37e93..d23fcc6 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
-static void init_proc_POWER8(CPUPPCState *env)
+static void get_spr_power8_branch_control(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- gen_spr_book3s_ids(env);
- gen_spr_book3s_common(env);
- gen_spr_amr(env);
- gen_spr_book3s_vr(env);
- gen_spr_book3s_lpar(env);
- gen_spr_book3s_purr(env);
- gen_spr_book3s_debug(env);
- gen_spr_book3s_pmu(env);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif /* !CONFIG_USER_ONLY */
- init_excp_POWER7(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- ppcPOWER7_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
-
spr_register(env, SPR_TAR, "TAR",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ spr_register(env, SPR_BESCRS, "BESCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRSU, "BESCRSU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRR, "BESCRR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRRU, "BESCRRU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_EBBHR, "EBBHR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBHR, 0x00000000);
+ spr_register_kvm(env, SPR_EBBRR, "EBBRR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBRR, 0x00000000);
+ spr_register_kvm(env, SPR_BESCR, "BESCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_BESCR, 0x00000000);
+}
+
+static void get_spr_power8_tm(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_TFHAR, "TFHAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TFHAR, 0x00000000);
+ spr_register_kvm(env, SPR_TFIAR, "TFIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TFIAR, 0x00000000);
+ spr_register_kvm(env, SPR_TEXASR, "TEXASR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TEXASR, 0x00000000);
+ spr_register(env, SPR_TEXASRU, "TEXASRU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void init_proc_POWER8(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_book3s_ids(env);
+ gen_spr_book3s_common(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_vr(env);
+ gen_spr_book3s_lpar(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_book3s_debug(env);
+ gen_spr_book3s_pmu(env);
+#if !defined(CONFIG_USER_ONLY)
+ env->slb_nr = 32;
+#endif /* !CONFIG_USER_ONLY */
+ init_excp_POWER7(env);
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ ppcPOWER7_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
+
+ get_spr_power8_branch_control(env);
+ get_spr_power8_tm(env);
+ spr_register(env, SPR_POWER_MMCR2, "MMCR2",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_UMMCR2, "UMMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR2, 0x00000000);
+ spr_register_kvm(env, SPR_FSCR, "FSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_FSCR, 0x00000000);
+ spr_register_kvm(env, SPR_MMCRS, "MMCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRS, 0x00000000);
}
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs
2014-05-21 6:20 ` [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs Alexey Kardashevskiy
@ 2014-05-21 10:47 ` Alexander Graf
2014-05-21 18:08 ` Tom Musta
1 sibling, 0 replies; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 10:47 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 08:20, Alexey Kardashevskiy wrote:
> This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/
> EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs.
>
> This adds MMCR2/FSCR/MMCRS SPRs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 15 ++++++
> target-ppc/translate_init.c | 123 ++++++++++++++++++++++++++++++++++----------
> 2 files changed, 112 insertions(+), 26 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 262cf0f..72ed763 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_EIE (0x050)
> #define SPR_MPC_EID (0x051)
> #define SPR_MPC_NRI (0x052)
> +#define SPR_TFHAR (0x080)
> +#define SPR_TFIAR (0x081)
> +#define SPR_TEXASR (0x082)
> +#define SPR_TEXASRU (0x083)
> #define SPR_UCTRL (0x088)
> #define SPR_MPC_CMPA (0x090)
> #define SPR_MPC_CMPB (0x091)
> @@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_CTRL (0x098)
> #define SPR_MPC_CMPE (0x098)
> #define SPR_MPC_CMPF (0x099)
> +#define SPR_FSCR (0x099)
> #define SPR_MPC_CMPG (0x09A)
> #define SPR_MPC_CMPH (0x09B)
> #define SPR_MPC_LCTRL1 (0x09C)
> @@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MI_CTR (0x300)
> #define SPR_PERF1 (0x301)
> #define SPR_RCPU_MI_RBA1 (0x301)
> +#define SPR_POWER_UMMCR2 (0x301)
> #define SPR_PERF2 (0x302)
> #define SPR_RCPU_MI_RBA2 (0x302)
> #define SPR_MPC_MI_AP (0x302)
> @@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MD_TW (0x30F)
> #define SPR_UPERF0 (0x310)
> #define SPR_UPERF1 (0x311)
> +#define SPR_POWER_MMCR2 (0x311)
> #define SPR_UPERF2 (0x312)
> #define SPR_MMCRA (0x312)
> #define SPR_UPERF3 (0x313)
> @@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_UPERFF (0x31F)
> #define SPR_RCPU_MI_RA0 (0x320)
> #define SPR_MPC_MI_DBCAM (0x320)
> +#define SPR_BESCRS (0x320)
> #define SPR_RCPU_MI_RA1 (0x321)
> #define SPR_MPC_MI_DBRAM0 (0x321)
> +#define SPR_BESCRSU (0x321)
> #define SPR_RCPU_MI_RA2 (0x322)
> #define SPR_MPC_MI_DBRAM1 (0x322)
> +#define SPR_BESCRR (0x322)
> #define SPR_RCPU_MI_RA3 (0x323)
> +#define SPR_BESCRRU (0x323)
> +#define SPR_EBBHR (0x324)
> +#define SPR_EBBRR (0x325)
> +#define SPR_BESCR (0x326)
> #define SPR_RCPU_L2U_RA0 (0x328)
> #define SPR_MPC_MD_DBCAM (0x328)
> #define SPR_RCPU_L2U_RA1 (0x329)
> @@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_440_ITV3 (0x377)
> #define SPR_440_CCR1 (0x378)
> #define SPR_DCRIPR (0x37B)
> +#define SPR_MMCRS (0x37E)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 3c37e93..d23fcc6 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> }
>
> -static void init_proc_POWER8(CPUPPCState *env)
> +static void get_spr_power8_branch_control(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - gen_spr_book3s_ids(env);
> - gen_spr_book3s_common(env);
> - gen_spr_amr(env);
> - gen_spr_book3s_vr(env);
> - gen_spr_book3s_lpar(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_book3s_debug(env);
> - gen_spr_book3s_pmu(env);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> -#endif /* !CONFIG_USER_ONLY */
> - init_excp_POWER7(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> -
> - /* Allocate hardware IRQ controller */
> - ppcPOWER7_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -
> spr_register(env, SPR_TAR, "TAR",
> &spr_read_generic, &spr_write_generic,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> +
> + spr_register(env, SPR_BESCRS, "BESCRS",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
Please introduce a special helper for these that checks whether FSCR.EBB
== 1 and injects a facility interrupt if not.
Alex
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs
2014-05-21 6:20 ` [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs Alexey Kardashevskiy
2014-05-21 10:47 ` Alexander Graf
@ 2014-05-21 18:08 ` Tom Musta
1 sibling, 0 replies; 29+ messages in thread
From: Tom Musta @ 2014-05-21 18:08 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
> This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/
> EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs.
>
> This adds MMCR2/FSCR/MMCRS SPRs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 15 ++++++
> target-ppc/translate_init.c | 123 ++++++++++++++++++++++++++++++++++----------
> 2 files changed, 112 insertions(+), 26 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 262cf0f..72ed763 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_EIE (0x050)
> #define SPR_MPC_EID (0x051)
> #define SPR_MPC_NRI (0x052)
> +#define SPR_TFHAR (0x080)
> +#define SPR_TFIAR (0x081)
> +#define SPR_TEXASR (0x082)
> +#define SPR_TEXASRU (0x083)
> #define SPR_UCTRL (0x088)
> #define SPR_MPC_CMPA (0x090)
> #define SPR_MPC_CMPB (0x091)
> @@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_CTRL (0x098)
> #define SPR_MPC_CMPE (0x098)
> #define SPR_MPC_CMPF (0x099)
> +#define SPR_FSCR (0x099)
> #define SPR_MPC_CMPG (0x09A)
> #define SPR_MPC_CMPH (0x09B)
> #define SPR_MPC_LCTRL1 (0x09C)
> @@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MI_CTR (0x300)
> #define SPR_PERF1 (0x301)
> #define SPR_RCPU_MI_RBA1 (0x301)
> +#define SPR_POWER_UMMCR2 (0x301)
> #define SPR_PERF2 (0x302)
> #define SPR_RCPU_MI_RBA2 (0x302)
> #define SPR_MPC_MI_AP (0x302)
> @@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MD_TW (0x30F)
> #define SPR_UPERF0 (0x310)
> #define SPR_UPERF1 (0x311)
> +#define SPR_POWER_MMCR2 (0x311)
> #define SPR_UPERF2 (0x312)
> #define SPR_MMCRA (0x312)
> #define SPR_UPERF3 (0x313)
> @@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_UPERFF (0x31F)
> #define SPR_RCPU_MI_RA0 (0x320)
> #define SPR_MPC_MI_DBCAM (0x320)
> +#define SPR_BESCRS (0x320)
> #define SPR_RCPU_MI_RA1 (0x321)
> #define SPR_MPC_MI_DBRAM0 (0x321)
> +#define SPR_BESCRSU (0x321)
> #define SPR_RCPU_MI_RA2 (0x322)
> #define SPR_MPC_MI_DBRAM1 (0x322)
> +#define SPR_BESCRR (0x322)
> #define SPR_RCPU_MI_RA3 (0x323)
> +#define SPR_BESCRRU (0x323)
> +#define SPR_EBBHR (0x324)
> +#define SPR_EBBRR (0x325)
> +#define SPR_BESCR (0x326)
> #define SPR_RCPU_L2U_RA0 (0x328)
> #define SPR_MPC_MD_DBCAM (0x328)
> #define SPR_RCPU_L2U_RA1 (0x329)
> @@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_440_ITV3 (0x377)
> #define SPR_440_CCR1 (0x378)
> #define SPR_DCRIPR (0x37B)
> +#define SPR_MMCRS (0x37E)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 3c37e93..d23fcc6 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> }
>
> -static void init_proc_POWER8(CPUPPCState *env)
> +static void get_spr_power8_branch_control(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - gen_spr_book3s_ids(env);
> - gen_spr_book3s_common(env);
> - gen_spr_amr(env);
> - gen_spr_book3s_vr(env);
> - gen_spr_book3s_lpar(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_book3s_debug(env);
> - gen_spr_book3s_pmu(env);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> -#endif /* !CONFIG_USER_ONLY */
> - init_excp_POWER7(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> -
> - /* Allocate hardware IRQ controller */
> - ppcPOWER7_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -
> spr_register(env, SPR_TAR, "TAR",
> &spr_read_generic, &spr_write_generic,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> +
> + spr_register(env, SPR_BESCRS, "BESCRS",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_BESCRSU, "BESCRSU",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_BESCRR, "BESCRR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_BESCRRU, "BESCRRU",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register_kvm(env, SPR_EBBHR, "EBBHR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_EBBHR, 0x00000000);
> + spr_register_kvm(env, SPR_EBBRR, "EBBRR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_EBBRR, 0x00000000);
> + spr_register_kvm(env, SPR_BESCR, "BESCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_BESCR, 0x00000000);
> +}
These are all user-mode accessible, no?
> +
> +static void get_spr_power8_tm(CPUPPCState *env)
> +{
> + spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_TFHAR, 0x00000000);
> + spr_register_kvm(env, SPR_TFIAR, "TFIAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_TFIAR, 0x00000000);
> + spr_register_kvm(env, SPR_TEXASR, "TEXASR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_TEXASR, 0x00000000);
> + spr_register(env, SPR_TEXASRU, "TEXASRU",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
Same comment.
Also, the xxxU SPRs numbers refer to the upper half of 64-bit SPRs. These are necessary
to support access on 32-bit implementations. It seems like some special spr access routines
are required to support this.
> +
> +static void init_proc_POWER8(CPUPPCState *env)
> +{
> + gen_spr_ne_601(env);
> + gen_spr_7xx(env);
> + /* Time base */
> + gen_tbl(env);
> + gen_spr_book3s_ids(env);
> + gen_spr_book3s_common(env);
> + gen_spr_amr(env);
> + gen_spr_book3s_vr(env);
> + gen_spr_book3s_lpar(env);
> + gen_spr_book3s_purr(env);
> + gen_spr_book3s_debug(env);
> + gen_spr_book3s_pmu(env);
> +#if !defined(CONFIG_USER_ONLY)
> + env->slb_nr = 32;
> +#endif /* !CONFIG_USER_ONLY */
> + init_excp_POWER7(env);
> + env->dcache_line_size = 128;
> + env->icache_line_size = 128;
> +
> + /* Allocate hardware IRQ controller */
> + ppcPOWER7_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
> +
> + get_spr_power8_branch_control(env);
> + get_spr_power8_tm(env);
> + spr_register(env, SPR_POWER_MMCR2, "MMCR2",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register_kvm(env, SPR_POWER_UMMCR2, "UMMCR2",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCR2, 0x00000000);
> + spr_register_kvm(env, SPR_FSCR, "FSCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_FSCR, 0x00000000);
> + spr_register_kvm(env, SPR_MMCRS, "MMCRS",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCRS, 0x00000000);
> }
>
> POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>
Fix these also.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (4 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 10:53 ` Alexander Graf
2014-05-21 6:20 ` [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration Alexey Kardashevskiy
` (2 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d23fcc6..82b502a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7767,10 +7767,10 @@ static void gen_spr_book3s_pmu(CPUPPCState *env)
static void gen_spr_book3s_vr(CPUPPCState *env)
{
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_VRSAVE, 0x00000000);
}
static void gen_spr_book3s_lpar(CPUPPCState *env)
@@ -7799,10 +7799,10 @@ static void gen_spr_book3s_common(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x80800000);
- spr_register(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PPR, 0x00000000);
}
static void init_proc_POWER7 (CPUPPCState *env)
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration
2014-05-21 6:20 ` [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
@ 2014-05-21 10:53 ` Alexander Graf
0 siblings, 0 replies; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 10:53 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 08:20, Alexey Kardashevskiy wrote:
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Patch description missing.
Alex
> ---
> target-ppc/translate_init.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index d23fcc6..82b502a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7767,10 +7767,10 @@ static void gen_spr_book3s_pmu(CPUPPCState *env)
>
> static void gen_spr_book3s_vr(CPUPPCState *env)
> {
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> + spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_VRSAVE, 0x00000000);
> }
>
> static void gen_spr_book3s_lpar(CPUPPCState *env)
> @@ -7799,10 +7799,10 @@ static void gen_spr_book3s_common(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, SPR_NOACCESS,
> 0x80800000);
> - spr_register(env, SPR_PPR, "PPR",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> + spr_register_kvm(env, SPR_PPR, "PPR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PPR, 0x00000000);
> }
>
> static void init_proc_POWER7 (CPUPPCState *env)
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (5 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 6/9] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 18:11 ` Tom Musta
2014-05-21 6:20 ` [Qemu-devel] [PATCH 8/9] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
8 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds migration support for registers saved before transaction started.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 19 +++++++++++++++++++
target-ppc/kvm.c | 38 ++++++++++++++++++++++++++++++++++++++
target-ppc/machine.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 72ed763..52baf20 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -426,6 +426,9 @@ struct ppc_slb_t {
#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_SHV 60 /* hypervisor state hflags */
+#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
+#define MSR_TS1 33
+#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */
#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
@@ -502,6 +505,8 @@ struct ppc_slb_t {
#define msr_pmm ((env->msr >> MSR_PMM) & 1)
#define msr_ri ((env->msr >> MSR_RI) & 1)
#define msr_le ((env->msr >> MSR_LE) & 1)
+#define msr_ts ((env->msr >> MSR_TS1) & 3)
+
/* Hypervisor bit is more specific */
#if defined(TARGET_PPC64)
#define MSR_HVB (1ULL << MSR_SHV)
@@ -1081,6 +1086,20 @@ struct CPUPPCState {
*/
uint8_t fit_period[4];
uint8_t wdt_period[4];
+
+ /* Transactional memory state */
+ target_ulong tm_gpr[32];
+ ppc_avr_t tm_vsr[64];
+ uint64_t tm_cr;
+ uint64_t tm_lr;
+ uint64_t tm_ctr;
+ uint64_t tm_fpscr;
+ uint64_t tm_amr;
+ uint64_t tm_ppr;
+ uint64_t tm_vrsave;
+ uint32_t tm_vscr;
+ uint64_t tm_dscr;
+ uint64_t tm_tar;
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index ca31027..6f10654 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -861,6 +861,25 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
#ifdef TARGET_PPC64
+ if (msr_ts) {
+ for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
+ }
+ for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
+ }
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
+ }
+
if (cap_papr) {
if (kvm_put_vpa(cs) < 0) {
DPRINTF("Warning: Unable to set VPA information to KVM\n");
@@ -1087,6 +1106,25 @@ int kvm_arch_get_registers(CPUState *cs)
}
#ifdef TARGET_PPC64
+ if (msr_ts) {
+ for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
+ }
+ for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
+ }
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
+ }
+
if (cap_papr) {
if (kvm_get_vpa(cs) < 0) {
DPRINTF("Warning: Unable to get VPA information from KVM\n");
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index df7cfc5..9c0e697 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -252,6 +252,38 @@ static const VMStateDescription vmstate_vsx = {
},
};
+#ifdef TARGET_PPC64
+/* Transactional memory state */
+static bool tm_needed(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+ return msr_ts;
+}
+
+static const VMStateDescription vmstate_tm = {
+ .name = "cpu/tm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
+ VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
+ VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
+ VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
+ VMSTATE_END_OF_LIST()
+ },
+};
+#endif
+
static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
@@ -522,6 +554,9 @@ const VMStateDescription vmstate_ppc_cpu = {
.needed = sr_needed,
} , {
#ifdef TARGET_PPC64
+ .vmsd = &vmstate_tm,
+ .needed = tm_needed,
+ } , {
.vmsd = &vmstate_slb,
.needed = slb_needed,
} , {
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration
2014-05-21 6:20 ` [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration Alexey Kardashevskiy
@ 2014-05-21 18:11 ` Tom Musta
2014-05-22 2:50 ` Alexey Kardashevskiy
0 siblings, 1 reply; 29+ messages in thread
From: Tom Musta @ 2014-05-21 18:11 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
> This adds migration support for registers saved before transaction started.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 19 +++++++++++++++++++
> target-ppc/kvm.c | 38 ++++++++++++++++++++++++++++++++++++++
> target-ppc/machine.c | 35 +++++++++++++++++++++++++++++++++++
> 3 files changed, 92 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 72ed763..52baf20 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -426,6 +426,9 @@ struct ppc_slb_t {
> #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
> #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
> #define MSR_SHV 60 /* hypervisor state hflags */
> +#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
> +#define MSR_TS1 33
> +#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
> #define MSR_CM 31 /* Computation mode for BookE hflags */
> #define MSR_ICM 30 /* Interrupt computation mode for BookE */
> #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
> @@ -502,6 +505,8 @@ struct ppc_slb_t {
> #define msr_pmm ((env->msr >> MSR_PMM) & 1)
> #define msr_ri ((env->msr >> MSR_RI) & 1)
> #define msr_le ((env->msr >> MSR_LE) & 1)
> +#define msr_ts ((env->msr >> MSR_TS1) & 3)
> +
> /* Hypervisor bit is more specific */
> #if defined(TARGET_PPC64)
> #define MSR_HVB (1ULL << MSR_SHV)
> @@ -1081,6 +1086,20 @@ struct CPUPPCState {
> */
> uint8_t fit_period[4];
> uint8_t wdt_period[4];
> +
> + /* Transactional memory state */
> + target_ulong tm_gpr[32];
> + ppc_avr_t tm_vsr[64];
> + uint64_t tm_cr;
> + uint64_t tm_lr;
> + uint64_t tm_ctr;
> + uint64_t tm_fpscr;
> + uint64_t tm_amr;
> + uint64_t tm_ppr;
> + uint64_t tm_vrsave;
> + uint32_t tm_vscr;
> + uint64_t tm_dscr;
> + uint64_t tm_tar;
> };
>
> #define SET_FIT_PERIOD(a_, b_, c_, d_) \
> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
> index ca31027..6f10654 100644
> --- a/target-ppc/kvm.c
> +++ b/target-ppc/kvm.c
> @@ -861,6 +861,25 @@ int kvm_arch_put_registers(CPUState *cs, int level)
> }
>
> #ifdef TARGET_PPC64
> + if (msr_ts) {
> + for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
> + }
> + for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
> + }
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
> + }
> +
> if (cap_papr) {
> if (kvm_put_vpa(cs) < 0) {
> DPRINTF("Warning: Unable to set VPA information to KVM\n");
> @@ -1087,6 +1106,25 @@ int kvm_arch_get_registers(CPUState *cs)
> }
>
> #ifdef TARGET_PPC64
> + if (msr_ts) {
> + for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
> + }
> + for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
> + }
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
> + }
> +
> if (cap_papr) {
> if (kvm_get_vpa(cs) < 0) {
> DPRINTF("Warning: Unable to get VPA information from KVM\n");
> diff --git a/target-ppc/machine.c b/target-ppc/machine.c
> index df7cfc5..9c0e697 100644
> --- a/target-ppc/machine.c
> +++ b/target-ppc/machine.c
> @@ -252,6 +252,38 @@ static const VMStateDescription vmstate_vsx = {
> },
> };
>
> +#ifdef TARGET_PPC64
> +/* Transactional memory state */
> +static bool tm_needed(void *opaque)
> +{
> + PowerPCCPU *cpu = opaque;
> + CPUPPCState *env = &cpu->env;
> + return msr_ts;
> +}
> +
> +static const VMStateDescription vmstate_tm = {
> + .name = "cpu/tm",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField []) {
> + VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
> + VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
> + VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
> + VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
> + VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
> + VMSTATE_END_OF_LIST()
> + },
> +};
> +#endif
> +
> static bool sr_needed(void *opaque)
> {
> #ifdef TARGET_PPC64
> @@ -522,6 +554,9 @@ const VMStateDescription vmstate_ppc_cpu = {
> .needed = sr_needed,
> } , {
> #ifdef TARGET_PPC64
> + .vmsd = &vmstate_tm,
> + .needed = tm_needed,
> + } , {
> .vmsd = &vmstate_slb,
> .needed = slb_needed,
> } , {
>
TM is not limited in the ISA to 64-bit implementations. Why restrict this to TARGET_PPC64?
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration
2014-05-21 18:11 ` Tom Musta
@ 2014-05-22 2:50 ` Alexey Kardashevskiy
2014-05-22 11:39 ` Tom Musta
0 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-22 2:50 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 05/22/2014 04:11 AM, Tom Musta wrote:
> On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
>> This adds migration support for registers saved before transaction started.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/cpu.h | 19 +++++++++++++++++++
>> target-ppc/kvm.c | 38 ++++++++++++++++++++++++++++++++++++++
>> target-ppc/machine.c | 35 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 92 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 72ed763..52baf20 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -426,6 +426,9 @@ struct ppc_slb_t {
>> #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
>> #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
>> #define MSR_SHV 60 /* hypervisor state hflags */
>> +#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
>> +#define MSR_TS1 33
>> +#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
>> #define MSR_CM 31 /* Computation mode for BookE hflags */
>> #define MSR_ICM 30 /* Interrupt computation mode for BookE */
>> #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
>> @@ -502,6 +505,8 @@ struct ppc_slb_t {
>> #define msr_pmm ((env->msr >> MSR_PMM) & 1)
>> #define msr_ri ((env->msr >> MSR_RI) & 1)
>> #define msr_le ((env->msr >> MSR_LE) & 1)
>> +#define msr_ts ((env->msr >> MSR_TS1) & 3)
>> +
>> /* Hypervisor bit is more specific */
>> #if defined(TARGET_PPC64)
>> #define MSR_HVB (1ULL << MSR_SHV)
>> @@ -1081,6 +1086,20 @@ struct CPUPPCState {
>> */
>> uint8_t fit_period[4];
>> uint8_t wdt_period[4];
>> +
>> + /* Transactional memory state */
>> + target_ulong tm_gpr[32];
>> + ppc_avr_t tm_vsr[64];
>> + uint64_t tm_cr;
>> + uint64_t tm_lr;
>> + uint64_t tm_ctr;
>> + uint64_t tm_fpscr;
>> + uint64_t tm_amr;
>> + uint64_t tm_ppr;
>> + uint64_t tm_vrsave;
>> + uint32_t tm_vscr;
>> + uint64_t tm_dscr;
>> + uint64_t tm_tar;
>> };
>>
>> #define SET_FIT_PERIOD(a_, b_, c_, d_) \
>> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
>> index ca31027..6f10654 100644
>> --- a/target-ppc/kvm.c
>> +++ b/target-ppc/kvm.c
>> @@ -861,6 +861,25 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>> }
>>
>> #ifdef TARGET_PPC64
>> + if (msr_ts) {
>> + for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
>> + }
>> + for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
>> + }
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
>> + kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
>> + }
>> +
>> if (cap_papr) {
>> if (kvm_put_vpa(cs) < 0) {
>> DPRINTF("Warning: Unable to set VPA information to KVM\n");
>> @@ -1087,6 +1106,25 @@ int kvm_arch_get_registers(CPUState *cs)
>> }
>>
>> #ifdef TARGET_PPC64
>> + if (msr_ts) {
>> + for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
>> + }
>> + for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
>> + }
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
>> + kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
>> + }
>> +
>> if (cap_papr) {
>> if (kvm_get_vpa(cs) < 0) {
>> DPRINTF("Warning: Unable to get VPA information from KVM\n");
>> diff --git a/target-ppc/machine.c b/target-ppc/machine.c
>> index df7cfc5..9c0e697 100644
>> --- a/target-ppc/machine.c
>> +++ b/target-ppc/machine.c
>> @@ -252,6 +252,38 @@ static const VMStateDescription vmstate_vsx = {
>> },
>> };
>>
>> +#ifdef TARGET_PPC64
>> +/* Transactional memory state */
>> +static bool tm_needed(void *opaque)
>> +{
>> + PowerPCCPU *cpu = opaque;
>> + CPUPPCState *env = &cpu->env;
>> + return msr_ts;
>> +}
>> +
>> +static const VMStateDescription vmstate_tm = {
>> + .name = "cpu/tm",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField []) {
>> + VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
>> + VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
>> + VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
>> + VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
>> + VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
>> + VMSTATE_END_OF_LIST()
>> + },
>> +};
>> +#endif
>> +
>> static bool sr_needed(void *opaque)
>> {
>> #ifdef TARGET_PPC64
>> @@ -522,6 +554,9 @@ const VMStateDescription vmstate_ppc_cpu = {
>> .needed = sr_needed,
>> } , {
>> #ifdef TARGET_PPC64
>> + .vmsd = &vmstate_tm,
>> + .needed = tm_needed,
>> + } , {
>> .vmsd = &vmstate_slb,
>> .needed = slb_needed,
>> } , {
>>
>
>
> TM is not limited in the ISA to 64-bit implementations. Why restrict
> this to TARGET_PPC64?
TS/TM bits in MSR are in top 32bits which are unavailable for 32bit
machine, and we are emulating a machine here, this is pretty much why.
--
Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration
2014-05-22 2:50 ` Alexey Kardashevskiy
@ 2014-05-22 11:39 ` Tom Musta
0 siblings, 0 replies; 29+ messages in thread
From: Tom Musta @ 2014-05-22 11:39 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 5/21/2014 9:50 PM, Alexey Kardashevskiy wrote:
> On 05/22/2014 04:11 AM, Tom Musta wrote:
>> On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote:
>>> This adds migration support for registers saved before transaction started.
>>>
[ ... ]
>>
>>
>
>> TM is not limited in the ISA to 64-bit implementations. Why restrict
>> this to TARGET_PPC64?
>
> TS/TM bits in MSR are in top 32bits which are unavailable for 32bit
> machine, and we are emulating a machine here, this is pretty much why.
>
>
OK. This makes more sense to me now. Thanks.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH 8/9] spapr_hcall: Split h_set_mode()
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (6 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 6:20 ` [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
8 siblings, 0 replies; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other "resources" coming and this is going to becode ugly.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 67 +++++++++++++++++++++++++++-------------------------
1 file changed, 35 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 0bae053..443e2b6 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -709,46 +709,49 @@ static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr,
return H_SUCCESS;
}
+static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
+ target_ulong mflags,
+ target_ulong value1,
+ target_ulong value2)
+{
+ CPUState *cs;
+
+ if (value1) {
+ return H_P3;
+ }
+ if (value2) {
+ return H_P4;
+ }
+
+ switch (mflags) {
+ case H_SET_MODE_ENDIAN_BIG:
+ CPU_FOREACH(cs) {
+ set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
+ }
+ return H_SUCCESS;
+
+ case H_SET_MODE_ENDIAN_LITTLE:
+ CPU_FOREACH(cs) {
+ set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
+ }
+ return H_SUCCESS;
+ }
+
+ return H_UNSUPPORTED_FLAG;
+}
+
static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs;
- target_ulong mflags = args[0];
target_ulong resource = args[1];
- target_ulong value1 = args[2];
- target_ulong value2 = args[3];
target_ulong ret = H_P2;
- if (resource == H_SET_MODE_RESOURCE_LE) {
- if (value1) {
- ret = H_P3;
- goto out;
- }
- if (value2) {
- ret = H_P4;
- goto out;
- }
- switch (mflags) {
- case H_SET_MODE_ENDIAN_BIG:
- CPU_FOREACH(cs) {
- set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
- }
- ret = H_SUCCESS;
- break;
-
- case H_SET_MODE_ENDIAN_LITTLE:
- CPU_FOREACH(cs) {
- set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
- }
- ret = H_SUCCESS;
- break;
-
- default:
- ret = H_UNSUPPORTED_FLAG;
- }
+ switch (resource) {
+ case H_SET_MODE_RESOURCE_LE:
+ ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
+ break;
}
-out:
return ret;
}
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-05-21 6:20 [Qemu-devel] [PATCH 0/9] POWER8 patches Alexey Kardashevskiy
` (7 preceding siblings ...)
2014-05-21 6:20 ` [Qemu-devel] [PATCH 8/9] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
@ 2014-05-21 6:20 ` Alexey Kardashevskiy
2014-05-21 11:44 ` Alexander Graf
2014-05-21 12:26 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
8 siblings, 2 replies; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 6:20 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for TCG.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 5 +++++
target-ppc/cpu.h | 4 +++-
target-ppc/excp_helper.c | 7 +++++--
4 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 443e2b6..e586c8b 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -740,6 +740,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
return H_UNSUPPORTED_FLAG;
}
+static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
+ target_ulong mflags,
+ target_ulong value1,
+ target_ulong value2)
+{
+ CPUState *cs;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ target_ulong prefix;
+
+ if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
+ return H_P2;
+ }
+ if (value1) {
+ return H_P3;
+ }
+ if (value2) {
+ return H_P4;
+ }
+
+ switch (mflags) {
+ case H_SET_MODE_ADDR_TRANS_NONE:
+ prefix = 0;
+ break;
+ case H_SET_MODE_ADDR_TRANS_0001_8000:
+ prefix = 0x18000;
+ break;
+ case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
+ prefix = 0xC000000000004000;
+ break;
+ default:
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ CPU_FOREACH(cs) {
+ CPUPPCState *env = &POWERPC_CPU(cpu)->env;
+
+ set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
+ env->excp_prefix = prefix;
+ }
+
+ return H_SUCCESS;
+}
+
static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
@@ -750,6 +793,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
case H_SET_MODE_RESOURCE_LE:
ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
break;
+ case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
+ ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
+ args[2], args[3]);
+ break;
}
return ret;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 9f8bb89..8a5705a 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
#define H_SET_MODE_ENDIAN_BIG 0
#define H_SET_MODE_ENDIAN_LITTLE 1
+/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
+#define H_SET_MODE_ADDR_TRANS_NONE 0
+#define H_SET_MODE_ADDR_TRANS_0001_8000 2
+#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
+
/* VASI States */
#define H_VASI_INVALID 0
#define H_VASI_ENABLED 1
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 52baf20..f435d0a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -466,6 +466,8 @@ struct ppc_slb_t {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
#define LPCR_ILE (1 << (63-38))
+#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
+#define LPCR_AIL_SH (63-40)
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
@@ -1971,7 +1973,7 @@ enum {
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
- PPC2_ALTIVEC_207)
+ PPC2_ALTIVEC_207 | PPC2_ISA207S)
};
/*****************************************************************************/
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 4fa297d..de32319 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -614,8 +614,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
if (asrr1 != -1) {
env->spr[asrr1] = env->spr[srr1];
}
- /* If we disactivated any translation, flush TLBs */
- if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
+
+ if (env->spr[SPR_LPCR] & LPCR_AIL) {
+ new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
+ } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
+ /* If we disactivated any translation, flush TLBs */
tlb_flush(cs, 1);
}
--
1.9.rc0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-05-21 6:20 ` [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
@ 2014-05-21 11:44 ` Alexander Graf
2014-05-21 12:24 ` Alexey Kardashevskiy
2014-05-21 12:26 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
1 sibling, 1 reply; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 11:44 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 08:20, Alexey Kardashevskiy wrote:
> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>
> This defines AIL flags for LPCR special register.
>
> This changes @excp_prefix according to the mode, takes effect in TCG.
>
> This turns support of a new capability PPC2_ISA207S flag for TCG.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/spapr.h | 5 +++++
> target-ppc/cpu.h | 4 +++-
> target-ppc/excp_helper.c | 7 +++++--
> 4 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 443e2b6..e586c8b 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -740,6 +740,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
> return H_UNSUPPORTED_FLAG;
> }
>
> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
> + target_ulong mflags,
> + target_ulong value1,
> + target_ulong value2)
> +{
> + CPUState *cs;
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> + target_ulong prefix;
> +
> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
> + return H_P2;
> + }
> + if (value1) {
> + return H_P3;
> + }
> + if (value2) {
> + return H_P4;
> + }
> +
> + switch (mflags) {
> + case H_SET_MODE_ADDR_TRANS_NONE:
> + prefix = 0;
> + break;
> + case H_SET_MODE_ADDR_TRANS_0001_8000:
> + prefix = 0x18000;
> + break;
> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
> + prefix = 0xC000000000004000;
> + break;
> + default:
> + return H_UNSUPPORTED_FLAG;
> + }
> +
> + CPU_FOREACH(cs) {
> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
> +
> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
> + env->excp_prefix = prefix;
I think it makes sense to run this on every vcpu thread individually to
ensure they all are updated after the hcall has finished.
Alex
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-05-21 11:44 ` Alexander Graf
@ 2014-05-21 12:24 ` Alexey Kardashevskiy
2014-05-21 12:25 ` Alexander Graf
0 siblings, 1 reply; 29+ messages in thread
From: Alexey Kardashevskiy @ 2014-05-21 12:24 UTC (permalink / raw)
To: Alexander Graf, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 05/21/2014 09:44 PM, Alexander Graf wrote:
>
> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
>> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>>
>> This defines AIL flags for LPCR special register.
>>
>> This changes @excp_prefix according to the mode, takes effect in TCG.
>>
>> This turns support of a new capability PPC2_ISA207S flag for TCG.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> hw/ppc/spapr_hcall.c | 47
>> +++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/spapr.h | 5 +++++
>> target-ppc/cpu.h | 4 +++-
>> target-ppc/excp_helper.c | 7 +++++--
>> 4 files changed, 60 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
>> index 443e2b6..e586c8b 100644
>> --- a/hw/ppc/spapr_hcall.c
>> +++ b/hw/ppc/spapr_hcall.c
>> @@ -740,6 +740,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU
>> *cpu,
>> return H_UNSUPPORTED_FLAG;
>> }
>> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
>> + target_ulong mflags,
>> + target_ulong value1,
>> + target_ulong value2)
>> +{
>> + CPUState *cs;
>> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>> + target_ulong prefix;
>> +
>> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
>> + return H_P2;
>> + }
>> + if (value1) {
>> + return H_P3;
>> + }
>> + if (value2) {
>> + return H_P4;
>> + }
>> +
>> + switch (mflags) {
>> + case H_SET_MODE_ADDR_TRANS_NONE:
>> + prefix = 0;
>> + break;
>> + case H_SET_MODE_ADDR_TRANS_0001_8000:
>> + prefix = 0x18000;
>> + break;
>> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
>> + prefix = 0xC000000000004000;
>> + break;
>> + default:
>> + return H_UNSUPPORTED_FLAG;
>> + }
>> +
>> + CPU_FOREACH(cs) {
>> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
>> +
>> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
>> + env->excp_prefix = prefix;
>
> I think it makes sense to run this on every vcpu thread individually to
> ensure they all are updated after the hcall has finished.
Sorry, I do not get it. set_spr() calls run_on_cpu(). What is missing?
--
Alexey
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-05-21 12:24 ` Alexey Kardashevskiy
@ 2014-05-21 12:25 ` Alexander Graf
0 siblings, 0 replies; 29+ messages in thread
From: Alexander Graf @ 2014-05-21 12:25 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: Tom Musta, qemu-ppc
On 21.05.14 14:24, Alexey Kardashevskiy wrote:
> On 05/21/2014 09:44 PM, Alexander Graf wrote:
>> On 21.05.14 08:20, Alexey Kardashevskiy wrote:
>>> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
>>> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>>>
>>> This defines AIL flags for LPCR special register.
>>>
>>> This changes @excp_prefix according to the mode, takes effect in TCG.
>>>
>>> This turns support of a new capability PPC2_ISA207S flag for TCG.
>>>
>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>> ---
>>> hw/ppc/spapr_hcall.c | 47
>>> +++++++++++++++++++++++++++++++++++++++++++++++
>>> include/hw/ppc/spapr.h | 5 +++++
>>> target-ppc/cpu.h | 4 +++-
>>> target-ppc/excp_helper.c | 7 +++++--
>>> 4 files changed, 60 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
>>> index 443e2b6..e586c8b 100644
>>> --- a/hw/ppc/spapr_hcall.c
>>> +++ b/hw/ppc/spapr_hcall.c
>>> @@ -740,6 +740,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU
>>> *cpu,
>>> return H_UNSUPPORTED_FLAG;
>>> }
>>> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
>>> + target_ulong mflags,
>>> + target_ulong value1,
>>> + target_ulong value2)
>>> +{
>>> + CPUState *cs;
>>> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>>> + target_ulong prefix;
>>> +
>>> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
>>> + return H_P2;
>>> + }
>>> + if (value1) {
>>> + return H_P3;
>>> + }
>>> + if (value2) {
>>> + return H_P4;
>>> + }
>>> +
>>> + switch (mflags) {
>>> + case H_SET_MODE_ADDR_TRANS_NONE:
>>> + prefix = 0;
>>> + break;
>>> + case H_SET_MODE_ADDR_TRANS_0001_8000:
>>> + prefix = 0x18000;
>>> + break;
>>> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
>>> + prefix = 0xC000000000004000;
>>> + break;
>>> + default:
>>> + return H_UNSUPPORTED_FLAG;
>>> + }
>>> +
>>> + CPU_FOREACH(cs) {
>>> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
>>> +
>>> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
>>> + env->excp_prefix = prefix;
>> I think it makes sense to run this on every vcpu thread individually to
>> ensure they all are updated after the hcall has finished.
> Sorry, I do not get it. set_spr() calls run_on_cpu(). What is missing?
Ah, I missed that part :). That works then.
Alex
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-05-21 6:20 ` [Qemu-devel] [PATCH 9/9] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-05-21 11:44 ` Alexander Graf
@ 2014-05-21 12:26 ` Greg Kurz
1 sibling, 0 replies; 29+ messages in thread
From: Greg Kurz @ 2014-05-21 12:26 UTC (permalink / raw)
To: Alexey Kardashevskiy; +Cc: Tom Musta, qemu-ppc, qemu-devel
On Wed, 21 May 2014 16:20:28 +1000
Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>
> This defines AIL flags for LPCR special register.
>
> This changes @excp_prefix according to the mode, takes effect in TCG.
>
> This turns support of a new capability PPC2_ISA207S flag for TCG.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/spapr.h | 5 +++++
> target-ppc/cpu.h | 4 +++-
> target-ppc/excp_helper.c | 7 +++++--
> 4 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 443e2b6..e586c8b 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -740,6 +740,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
> return H_UNSUPPORTED_FLAG;
> }
>
> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
> + target_ulong mflags,
> + target_ulong value1,
> + target_ulong value2)
> +{
> + CPUState *cs;
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> + target_ulong prefix;
> +
> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
> + return H_P2;
> + }
> + if (value1) {
> + return H_P3;
> + }
> + if (value2) {
> + return H_P4;
> + }
> +
> + switch (mflags) {
> + case H_SET_MODE_ADDR_TRANS_NONE:
> + prefix = 0;
> + break;
> + case H_SET_MODE_ADDR_TRANS_0001_8000:
> + prefix = 0x18000;
> + break;
> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
> + prefix = 0xC000000000004000;
> + break;
> + default:
> + return H_UNSUPPORTED_FLAG;
> + }
> +
> + CPU_FOREACH(cs) {
> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
> +
> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
> + env->excp_prefix = prefix;
> + }
> +
> + return H_SUCCESS;
> +}
> +
> static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
> target_ulong opcode, target_ulong *args)
> {
> @@ -750,6 +793,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
> case H_SET_MODE_RESOURCE_LE:
> ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
> break;
> + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
> + ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
> + args[2], args[3]);
> + break;
> }
>
> return ret;
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 9f8bb89..8a5705a 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
> #define H_SET_MODE_ENDIAN_BIG 0
> #define H_SET_MODE_ENDIAN_LITTLE 1
>
> +/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
> +#define H_SET_MODE_ADDR_TRANS_NONE 0
> +#define H_SET_MODE_ADDR_TRANS_0001_8000 2
> +#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
> +
> /* VASI States */
> #define H_VASI_INVALID 0
> #define H_VASI_ENABLED 1
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 52baf20..f435d0a 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -466,6 +466,8 @@ struct ppc_slb_t {
> #define MSR_LE 0 /* Little-endian mode 1 hflags */
>
> #define LPCR_ILE (1 << (63-38))
> +#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
> +#define LPCR_AIL_SH (63-40)
>
A decision was recently taken to get rid of magic numbers. What about the following ?
#define LPCR_AIL_SHIFT (63-40)
#define LPCR_AIL_MASK (3 << LPCR_AIL_SHIFT)
> #define msr_sf ((env->msr >> MSR_SF) & 1)
> #define msr_isf ((env->msr >> MSR_ISF) & 1)
> @@ -1971,7 +1973,7 @@ enum {
> PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
> PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
> - PPC2_ALTIVEC_207)
> + PPC2_ALTIVEC_207 | PPC2_ISA207S)
> };
>
> /*****************************************************************************/
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 4fa297d..de32319 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -614,8 +614,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> if (asrr1 != -1) {
> env->spr[asrr1] = env->spr[srr1];
> }
> - /* If we disactivated any translation, flush TLBs */
> - if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> +
> + if (env->spr[SPR_LPCR] & LPCR_AIL) {
> + new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
> + } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> + /* If we disactivated any translation, flush TLBs */
> tlb_flush(cs, 1);
> }
>
--
Gregory Kurz kurzgreg@fr.ibm.com
gkurz@linux.vnet.ibm.com
Software Engineer @ IBM/Meiosys http://www.ibm.com
Tel +33 (0)562 165 496
"Anarchy is about taking complete responsibility for yourself."
Alan Moore.
^ permalink raw reply [flat|nested] 29+ messages in thread