From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wn1sh-0007N8-Cj for qemu-devel@nongnu.org; Wed, 21 May 2014 04:28:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wn1sV-0000Xv-9W for qemu-devel@nongnu.org; Wed, 21 May 2014 04:28:11 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:45809) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wn1sU-0000XE-Gj for qemu-devel@nongnu.org; Wed, 21 May 2014 04:27:59 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 21 May 2014 18:27:53 +1000 From: Alexey Kardashevskiy Date: Wed, 21 May 2014 18:27:40 +1000 Message-Id: <1400660862-20455-8-git-send-email-aik@ozlabs.ru> In-Reply-To: <1400660862-20455-1-git-send-email-aik@ozlabs.ru> References: <1400660862-20455-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH v2 7/9] spapr: Limit threads per core according to current compatibility mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, Alexander Graf This puts a limit to the number of threads per core based on the current compatibility mode. Although PowerISA specs do not specify the maximum threads per core number, the linux guest still expects that PowerISA2.05-compatible CPU supports only 2 threads per core as this is what POWER6 (2.05 compliant CPU) implements, the same is for POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads). This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of threads which affects ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. The number of CPU nodesremains unchanged. Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr.c | 2 +- target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 27 +++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7082237..14c72d9 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -293,7 +293,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) } ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, - smp_threads); + ppc_get_compat_smt_threads(cpu)); if (ret < 0) { return ret; } diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d3b8236..7b465b8 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1122,6 +1122,7 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); void ppc_store_msr (CPUPPCState *env, target_ulong value); void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); +int ppc_get_compat_smt_threads(PowerPCCPU *cpu); int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version); /* Time-base and decrementer management */ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index faac74a..56d3b97 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8921,6 +8921,33 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) } } +int ppc_get_compat_smt_threads(PowerPCCPU *cpu) +{ + int ret = smp_threads; + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + + switch (cpu->cpu_version) { + case CPU_POWERPC_LOGICAL_2_05: + ret = 2; + break; + case CPU_POWERPC_LOGICAL_2_06: + ret = 4; + break; + case CPU_POWERPC_LOGICAL_2_07: + ret = 8; + break; + default: + if (pcc->pcr_mask & PCR_COMPAT_2_06) { + ret = 4; + } else if (pcc->pcr_mask & PCR_COMPAT_2_05) { + ret = 2; + } + break; + } + + return MIN(ret, smp_threads); +} + int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version) { int ret = 0; -- 1.9.rc0