From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wn2Ex-0001HO-IS for qemu-devel@nongnu.org; Wed, 21 May 2014 04:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wn2Es-0002BA-Oy for qemu-devel@nongnu.org; Wed, 21 May 2014 04:51:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:25212) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wn2Es-0002B2-Ew for qemu-devel@nongnu.org; Wed, 21 May 2014 04:51:06 -0400 From: Gerd Hoffmann Date: Wed, 21 May 2014 10:50:36 +0200 Message-Id: <1400662237-23743-2-git-send-email-kraxel@redhat.com> In-Reply-To: <1400662237-23743-1-git-send-email-kraxel@redhat.com> References: <1400662237-23743-1-git-send-email-kraxel@redhat.com> Subject: [Qemu-devel] [PULL 1/2] audio/intel-hda: support FIFORDY List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Stanislav Vorobiov , "Vassili Karpov (malc)" , Gerd Hoffmann From: Stanislav Vorobiov linux kernel 3.12 has changed intel-hda driver to always check for FIFORDY, this causes long hangs in guest since QEMU always has this bit set to 0. We now simply set it to 1 always, since we're synchronous anyway and always ready to receive the stream Signed-off-by: Stanislav Vorobiov Signed-off-by: Gerd Hoffmann --- hw/audio/intel-hda.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index d41f82c..9e075c0 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -574,7 +574,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint3 if (st->ctl & 0x01) { /* reset */ dprint(d, 1, "st #%d: reset\n", reg->stream); - st->ctl = 0; + st->ctl = SD_STS_FIFO_READY << 24; } if ((st->ctl & 0x02) != (old & 0x02)) { uint32_t stnr = (st->ctl >> 20) & 0x0f; @@ -829,6 +829,7 @@ static const struct IntelHDAReg regtab[] = { .wclear = 0x1c000000, \ .offset = offsetof(IntelHDAState, st[_i].ctl), \ .whandler = intel_hda_set_st_ctl, \ + .reset = SD_STS_FIFO_READY << 24 \ }, \ [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ .stream = _i, \ -- 1.8.3.1