From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44653) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndfa-0007jr-0Y for qemu-devel@nongnu.org; Thu, 22 May 2014 20:49:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WndfY-00072q-SZ for qemu-devel@nongnu.org; Thu, 22 May 2014 20:49:09 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:53125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WndfY-00072m-Jo for qemu-devel@nongnu.org; Thu, 22 May 2014 20:49:08 -0400 Received: by mail-pa0-f42.google.com with SMTP id rd3so3275345pab.29 for ; Thu, 22 May 2014 17:49:07 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 23 May 2014 10:42:06 +1000 Message-Id: <1400805738-11889-10-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 09/21] target-arm: Add SPSR entries for EL2/HYP and EL3/MON List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 4 +++- target-arm/helper.c | 4 ++++ target-arm/machine.c | 6 +++--- target-arm/translate.c | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 60414ac..5919dfd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -143,7 +143,7 @@ typedef struct CPUARMState { uint32_t spsr; /* Banked registers. */ - uint64_t banked_spsr[6]; + uint64_t banked_spsr[8]; uint32_t banked_r13[6]; uint32_t banked_r14[6]; @@ -563,7 +563,9 @@ enum arm_cpu_mode { ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_SVC = 0x13, + ARM_CPU_MODE_MON = 0x16, ARM_CPU_MODE_ABT = 0x17, + ARM_CPU_MODE_HYP = 0x1a, ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_SYS = 0x1f }; diff --git a/target-arm/helper.c b/target-arm/helper.c index bba7297..5e2eac3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3084,6 +3084,10 @@ int bank_number(int mode) return 4; case ARM_CPU_MODE_FIQ: return 5; + case ARM_CPU_MODE_HYP: + return 6; + case ARM_CPU_MODE_MON: + return 7; } hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 233e70d..3bcc7cc 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 19, - .minimum_version_id = 19, + .version_id = 20, + .minimum_version_id = 20, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -233,7 +233,7 @@ const VMStateDescription vmstate_arm_cpu = { .offset = 0, }, VMSTATE_UINT32(env.spsr, ARMCPU), - VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), + VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), diff --git a/target-arm/translate.c b/target-arm/translate.c index eb63bb5..15aa00b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11053,8 +11053,8 @@ void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) } static const char *cpu_mode_names[16] = { - "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", - "???", "???", "???", "und", "???", "???", "???", "sys" + "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", + "???", "???", "hyp", "und", "???", "???", "???", "sys" }; void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, -- 1.8.3.2