From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndj4-0003gf-3a for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wndiw-0008Bb-PT for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:46 -0400 Received: from mail-pb0-x230.google.com ([2607:f8b0:400e:c01::230]:58443) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndiw-0008BJ-GX for qemu-devel@nongnu.org; Thu, 22 May 2014 20:52:38 -0400 Received: by mail-pb0-f48.google.com with SMTP id rr13so3268175pbb.7 for ; Thu, 22 May 2014 17:52:37 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 23 May 2014 10:42:11 +1000 Message-Id: <1400805738-11889-15-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 14/21] target-arm: Register EL3 versions of ELR and SPSR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 81de010..cb7c964a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2090,6 +2090,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2344,6 +2357,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new * PMSA core later than the ARM946 will require that we -- 1.8.3.2