From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WndlF-00070q-Jb for qemu-devel@nongnu.org; Thu, 22 May 2014 20:55:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wndl6-0000RB-Lk for qemu-devel@nongnu.org; Thu, 22 May 2014 20:55:01 -0400 Received: from mail-yh0-x22b.google.com ([2607:f8b0:4002:c01::22b]:34818) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndl6-0000QV-He for qemu-devel@nongnu.org; Thu, 22 May 2014 20:54:52 -0400 Received: by mail-yh0-f43.google.com with SMTP id v1so3679422yhn.2 for ; Thu, 22 May 2014 17:54:52 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 23 May 2014 10:42:14 +1000 Message-Id: <1400805738-11889-18-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 17/21] target-arm: A64: Generalize ERET to various ELs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Adds support for ERET to and from AArch64 EL2 and 3. Signed-off-by: Edgar E. Iglesias --- target-arm/op_helper.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index e95a7f4..50a4157 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -386,13 +386,13 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) void HELPER(exception_return)(CPUARMState *env) { - unsigned int spsr_idx = aarch64_banked_spsr_index(1); + int cur_el = arm_current_pl(env); + unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); uint32_t spsr = env->banked_spsr[spsr_idx]; int new_el, i; - int cur_el = arm_current_pl(env); if (env->pstate & PSTATE_SP) { - env->sp_el[1] = env->xregs[31]; + env->sp_el[cur_el] = env->xregs[31]; } else { env->sp_el[0] = env->xregs[31]; } @@ -400,6 +400,7 @@ void HELPER(exception_return)(CPUARMState *env) env->exclusive_addr = -1; if (spsr & PSTATE_nRW) { + /* TODO: We currently assume EL1/2/3 are running in AArch64. */ env->aarch64 = 0; new_el = 0; env->uncached_cpsr = 0x10; @@ -429,7 +430,7 @@ void HELPER(exception_return)(CPUARMState *env) env->aarch64 = 1; pstate_write(env, spsr); env->xregs[31] = env->sp_el[new_el]; - env->pc = env->elr_el[1]; + env->pc = env->elr_el[cur_el]; } return; @@ -443,7 +444,7 @@ illegal_return: * no change to exception level, execution state or stack pointer */ env->pstate |= PSTATE_IL; - env->pc = env->elr_el[1]; + env->pc = env->elr_el[cur_el]; spsr &= PSTATE_NZCV | PSTATE_DAIF; spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); pstate_write(env, spsr); -- 1.8.3.2