From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndf0-0006mv-8c for qemu-devel@nongnu.org; Thu, 22 May 2014 20:48:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wndeu-0006xJ-9a for qemu-devel@nongnu.org; Thu, 22 May 2014 20:48:34 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:39219) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wndeu-0006x0-3W for qemu-devel@nongnu.org; Thu, 22 May 2014 20:48:28 -0400 Received: by mail-pa0-f43.google.com with SMTP id hz1so3252093pad.2 for ; Thu, 22 May 2014 17:48:27 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 23 May 2014 10:42:05 +1000 Message-Id: <1400805738-11889-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> References: <1400805738-11889-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 08/21] target-arm: A64: Add ELR entries for EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/machine.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ba1d495..60414ac 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -162,7 +162,7 @@ typedef struct CPUARMState { uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ - uint64_t elr_el[2]; /* AArch64 exception link regs */ + uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ /* System control coprocessor (cp15) */ diff --git a/target-arm/machine.c b/target-arm/machine.c index 7b18a90..233e70d 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 18, - .minimum_version_id = 18, + .version_id = 19, + .minimum_version_id = 19, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -238,7 +238,7 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), - VMSTATE_UINT64(env.elr_el[1], ARMCPU), + VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), /* The length-check must come before the arrays to avoid * incoming data possibly overflowing the array. -- 1.8.3.2