From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoNB2-0008EF-MX for qemu-devel@nongnu.org; Sat, 24 May 2014 21:24:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoNAu-0007v6-4O for qemu-devel@nongnu.org; Sat, 24 May 2014 21:24:40 -0400 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]:60058) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoNAt-0007v0-T4 for qemu-devel@nongnu.org; Sat, 24 May 2014 21:24:32 -0400 Received: by mail-pa0-f47.google.com with SMTP id lf10so5843474pab.34 for ; Sat, 24 May 2014 18:24:30 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sun, 25 May 2014 11:08:51 +1000 Message-Id: <1400980132-25949-23-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> References: <1400980132-25949-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 22/23] target-arm: A64: Register VBAR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, john.williams@xilinx.com, greg.bellows@linaro.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/helper.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b14fac5..3ccbd95 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -198,7 +198,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[2]; /* vector base address register */ + uint64_t vbar_el[3]; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 5a2073e..ebe735b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2077,6 +2077,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { REGINFO_SENTINEL }; +/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ +static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { + { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + REGINFO_SENTINEL +}; + static const ARMCPRegInfo v8_el2_cp_reginfo[] = { { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, @@ -2087,6 +2096,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, + { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, + .access = PL2_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), + .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2356,6 +2370,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); + } else { + /* If EL2 is missing but higher ELs are enabled, we need to + * register the no_el2 reginfos. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo); + } } if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, v8_el3_cp_reginfo); -- 1.8.3.2