From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl1F-0008D7-GQ for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:29:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrl13-0000Zy-KA for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:33 -0400 Received: from e23smtp04.au.ibm.com ([202.81.31.146]:52110) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl11-0000VC-JJ for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:21 -0400 Received: from /spool/local by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 3 Jun 2014 19:28:10 +1000 From: Alexey Kardashevskiy Date: Tue, 3 Jun 2014 19:27:35 +1000 Message-Id: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexey Kardashevskiy , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf Started as POWER7/8 SPRs patchset, this became a rework of book3s/970 CPU classes initialization. The aim is to boot little endian guests in TCG mode with -cpu POWER8 (ironically, POWER8 emulation still fails, debugging it now but most of the set is still valid). Individual patches have change logs. Please comment. Thanks! Alexey Kardashevskiy (29): target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs target-ppc: Merge 970FX and 970MP into a single 970 class target-ppc: Refactor PPC970 target-ppc: Copy and split gen_spr_7xx() for 970 target-ppc: Add "POWER" prefix to MMCRA PMU registers target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family target-ppc: Add PMC7/8 to 970 class target-ppc: Add HID4 SPR for PPC970 target-ppc: Introduce and reuse generalized init_proc_book3s_64() target-ppc: Remove check_pow_970FX target-ppc: Enable PMU SPRs migration target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers target-ppc: Move POWER8 TCE Address control (TAR) to a helper target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8 target-ppc: Switch POWER7/8 classes to use correct PMU SPRs target-ppc: Refactor class init for POWER7/8 target-ppc: Add POWER7's TIR SPR target-ppc: Add POWER8's FSCR SPR target-ppc: Enable FSCR facility check for TAR target-ppc: Add POWER8's MMCR2/MMCRS SPRs target-ppc: Add POWER8's TM SPRs KVM: target-ppc: Enable TM state migration target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs target-ppc: Enable PPR and VRSAVE SPRs migration target-ppc: Enable DABRX SPR and limit it to <=POWER7 spapr_hcall: Split h_set_mode() spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE hw/ppc/spapr_hcall.c | 114 +++-- include/hw/ppc/spapr.h | 5 + target-ppc/cpu-models.c | 14 +- target-ppc/cpu.h | 123 ++++- target-ppc/excp_helper.c | 12 +- target-ppc/helper.h | 2 + target-ppc/kvm.c | 38 ++ target-ppc/machine.c | 35 ++ target-ppc/misc_helper.c | 39 ++ target-ppc/translate.c | 7 + target-ppc/translate_init.c | 1053 ++++++++++++++++++++++++++----------------- 11 files changed, 953 insertions(+), 489 deletions(-) -- 2.0.0