From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl1V-0008Dx-Nz for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:29:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrl1A-0000fQ-CT for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:49 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:57231) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl18-0000bD-Lk for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:28 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 3 Jun 2014 19:28:21 +1000 From: Alexey Kardashevskiy Date: Tue, 3 Jun 2014 19:27:56 +1000 Message-Id: <1401787684-31895-22-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexey Kardashevskiy , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf This makes user-privileged read/write fail if TAR facility is not enabled in FSCR. Since this is the very first check for enabled in FSCR facility, this also adds gen_fscr_facility_check() for using in spr_write_tar()/ spr_read_tar(). Signed-off-by: Alexey Kardashevskiy --- target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 6f0c36b..9b83d56 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE { BOOK3S_CPU_POWER8 }; +static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, + int sprn, int cause) +{ + TCGv_i32 t1 = tcg_const_i32(bit); + TCGv_i32 t2 = tcg_const_i32(sprn); + TCGv_i32 t3 = tcg_const_i32(cause); + + gen_update_current_nip(opaque); + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); + + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + static int check_pow_970 (CPUPPCState *env) { if (env->spr[SPR_HID0] & 0x01C00000) { @@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env) 0x00000000); } +static void spr_read_tar(void *opaque, int gprn, int sprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_read_generic(opaque, gprn, sprn); +} + +static void spr_write_tar(void *opaque, int sprn, int gprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_write_generic(opaque, sprn, gprn); +} + static void gen_spr_power8_tce_address_control(CPUPPCState *env) { spr_register(env, SPR_TAR, "TAR", - &spr_read_generic, &spr_write_generic, + &spr_read_tar, &spr_write_tar, &spr_read_generic, &spr_write_generic, 0x00000000); } -- 2.0.0