From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl1N-0008DW-DR for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:29:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrl15-0000cC-S2 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:41 -0400 Received: from e23smtp09.au.ibm.com ([202.81.31.142]:41561) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrl12-0000Vi-Mp for qemu-devel@nongnu.org; Tue, 03 Jun 2014 05:28:23 -0400 Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 3 Jun 2014 19:28:11 +1000 From: Alexey Kardashevskiy Date: Tue, 3 Jun 2014 19:27:37 +1000 Message-Id: <1401787684-31895-3-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexey Kardashevskiy , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf The differences between classes were: 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all; 2. check_pow() callback, HID0 format is the same so should be the same 0x01C00000 which means "deep nap", "doze" and "nap" bits set; 3. LPCR - 970 does not have it but 970MP had one (by mistake). This fixes wrong differences and makes one 970 class. This fixes wrong registration of LPCR which is not present on 970. This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to 970 class as we do not emulate hypervisor in QEMU anyway. This does not remove check_pow_970FX now as it is still used by POWER5+ class, this will be addressed later. Signed-off-by: Alexey Kardashevskiy --- target-ppc/cpu-models.c | 14 +-- target-ppc/translate_init.c | 222 ++++---------------------------------------- 2 files changed, 23 insertions(+), 213 deletions(-) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 9a66c03..97a81d8 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -1142,19 +1142,19 @@ "POWER8 v1.0") POWERPC_DEF("970", CPU_POWERPC_970, 970, "PowerPC 970") - POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX, + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970, "PowerPC 970FX v1.0 (G5)") - POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX, + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970, "PowerPC 970FX v2.0 (G5)") - POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX, + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970, "PowerPC 970FX v2.1 (G5)") - POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX, + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970, "PowerPC 970FX v3.0 (G5)") - POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX, + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970, "PowerPC 970FX v3.1 (G5)") - POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP, + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970, "PowerPC 970MP v1.0") - POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP, + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970, "PowerPC 970MP v1.1") #if defined(TODO) POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970, diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index fa137af..2f40d0d 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7268,8 +7268,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) static int check_pow_970 (CPUPPCState *env) { - if (env->spr[SPR_HID0] & 0x00600000) + if (env->spr[SPR_HID0] & 0x01C00000) { return 1; + } return 0; } @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, 0x00000000); + + spr_register(env, SPR_CTRL, "SPR_CTRL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UCTRL, "SPR_UCTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); #if !defined(CONFIG_USER_ONLY) - env->slb_nr = 32; + env->slb_nr = 64; #endif init_excp_970(env); env->dcache_line_size = 128; @@ -7334,7 +7348,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI; pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_SHV) | (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_EE) | @@ -7371,209 +7384,6 @@ static int check_pow_970FX (CPUPPCState *env) return 0; } -static void init_proc_970FX (CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - 0x60000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_970_HID5, "HID5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - POWERPC970_HID5_INIT); - /* Memory management */ - /* XXX: not correct */ - gen_low_BATs(env); - spr_register(env, SPR_HIOR, "SPR_HIOR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_hior, &spr_write_hior, - 0x00000000); - spr_register(env, SPR_CTRL, "SPR_CTRL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_UCTRL, "SPR_UCTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#if !defined(CONFIG_USER_ONLY) - env->slb_nr = 64; -#endif - init_excp_970(env); - env->dcache_line_size = 128; - env->icache_line_size = 128; - /* Allocate hardware IRQ controller */ - ppc970_irq_init(env); - /* Can't find information on what this should be on reset. This - * value is the one used by 74xx processors. */ - vscr_init(env, 0x00010000); -} - -POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 970FX (aka G5)"; - pcc->init_proc = init_proc_970FX; - pcc->check_pow = check_pow_970FX; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_970; - pcc->bus_model = PPC_FLAGS_INPUT_970; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x10000; -} - -static int check_pow_970MP (CPUPPCState *env) -{ - if (env->spr[SPR_HID0] & 0x01C00000) - return 1; - - return 0; -} - -static void init_proc_970MP (CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - 0x60000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_970_HID5, "HID5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - POWERPC970_HID5_INIT); - /* XXX : not implemented */ - /* Memory management */ - /* XXX: not correct */ - gen_low_BATs(env); - spr_register(env, SPR_HIOR, "SPR_HIOR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_hior, &spr_write_hior, - 0x00000000); - /* Logical partitionning */ - spr_register_kvm(env, SPR_LPCR, "LPCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_LPCR, 0x00000000); -#if !defined(CONFIG_USER_ONLY) - env->slb_nr = 32; -#endif - init_excp_970(env); - env->dcache_line_size = 128; - env->icache_line_size = 128; - /* Allocate hardware IRQ controller */ - ppc970_irq_init(env); - /* Can't find information on what this should be on reset. This - * value is the one used by 74xx processors. */ - vscr_init(env, 0x00010000); -} - -POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 970 MP"; - pcc->init_proc = init_proc_970MP; - pcc->check_pow = check_pow_970MP; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_SHV) | - (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_970; - pcc->bus_model = PPC_FLAGS_INPUT_970; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x10000; -} - static void init_proc_power5plus(CPUPPCState *env) { gen_spr_ne_601(env); -- 2.0.0