From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
Tom Musta <tommusta@gmail.com>,
qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>,
Greg Kurz <gkurz@linux.vnet.ibm.com>
Subject: [Qemu-devel] [PATCH v5 19/30] target-ppc: Refactor class init for POWER7/8
Date: Wed, 4 Jun 2014 22:50:54 +1000 [thread overview]
Message-ID: <1401886265-6589-20-git-send-email-aik@ozlabs.ru> (raw)
In-Reply-To: <1401886265-6589-1-git-send-email-aik@ozlabs.ru>
This extends init_proc_book3s_64 to support POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
---
Changes:
v4:
* added g_assert_not_reached() to default path to catch errors earlier
---
target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++-----------------
1 file changed, 61 insertions(+), 39 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index df90439..7eb02ac 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7276,6 +7276,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
enum BOOK3S_CPU_TYPE {
BOOK3S_CPU_970,
BOOK3S_CPU_POWER5PLUS,
+ BOOK3S_CPU_POWER6,
+ BOOK3S_CPU_POWER7,
+ BOOK3S_CPU_POWER8
};
static int check_pow_970 (CPUPPCState *env)
@@ -7582,30 +7585,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_book3s_pmu_sup(env);
gen_spr_book3s_pmu_user(env);
gen_spr_book3s_dbg(env);
-
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
gen_spr_book3s_common(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
+ gen_low_BATs(env);
+ gen_spr_970_pmu_sup(env);
+ gen_spr_970_pmu_user(env);
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ gen_spr_book3s_ids(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_purr(env);
+ break;
+ default:
+ g_assert_not_reached();
+ }
if (version >= BOOK3S_CPU_POWER5PLUS) {
+ gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
} else {
gen_spr_970_lpar(env);
}
-
- gen_spr_970_dbg(env);
+ if (version == BOOK3S_CPU_970) {
+ gen_spr_970_dbg(env);
+ }
+ if (version >= BOOK3S_CPU_POWER6) {
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ }
+ if (version >= BOOK3S_CPU_POWER8) {
+ gen_spr_power8_tce_address_control(env);
+ }
#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ env->slb_nr = 64;
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ default:
+ env->slb_nr = 32;
+ break;
+ }
#endif
- init_excp_970(env);
+ /* Allocate hardware IRQ controller */
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ init_excp_970(env);
+ ppc970_irq_init(env);
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ init_excp_POWER7(env);
+ ppcPOWER7_irq_init(env);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
env->dcache_line_size = 128;
env->icache_line_size = 128;
- /* Allocate hardware IRQ controller */
- ppc970_irq_init(env);
}
static void init_proc_970(CPUPPCState *env)
@@ -7783,29 +7830,7 @@ static Property powerpc_servercpu_properties[] = {
static void init_proc_POWER7 (CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_book3s_altivec(env);
- /* Time base */
- gen_tbl(env);
- gen_spr_book3s_ids(env);
- gen_spr_book3s_purr(env);
- gen_spr_book3s_common(env);
- gen_spr_book3s_pmu_sup(env);
- gen_spr_book3s_pmu_user(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_amr(env);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
- init_excp_POWER7(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- ppcPOWER7_irq_init(env);
+ init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
}
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
@@ -7932,10 +7957,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
static void init_proc_POWER8(CPUPPCState *env)
{
- /* inherit P7 */
- init_proc_POWER7(env);
-
- gen_spr_power8_tce_address_control(env);
+ init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
}
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
--
2.0.0
next prev parent reply other threads:[~2014-06-04 12:52 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-04 12:50 [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 01/30] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 02/30] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 03/30] target-ppc: Refactor PPC970 Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 04/30] target-ppc: Make UCTRL a mirror of CTRL Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 05/30] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 06/30] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 07/30] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 08/30] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 09/30] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 10/30] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 11/30] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 12/30] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 13/30] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 14/30] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 15/30] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 16/30] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 17/30] target-ppc: Make use of gen_spr_power5p_lpar() " Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 18/30] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` Alexey Kardashevskiy [this message]
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 22/30] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 25/30] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 26/30] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 29/30] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 30/30] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-07-08 14:37 ` Peter Maydell
2014-07-08 14:45 ` Alexander Graf
2014-06-04 17:37 ` [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Tom Musta
2014-06-04 21:51 ` Alexander Graf
2014-06-04 23:37 ` Alexey Kardashevskiy
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