From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
Tom Musta <tommusta@gmail.com>,
qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>,
Greg Kurz <gkurz@linux.vnet.ibm.com>
Subject: [Qemu-devel] [PATCH v5 03/30] target-ppc: Refactor PPC970
Date: Wed, 4 Jun 2014 22:50:38 +1000 [thread overview]
Message-ID: <1401886265-6589-4-git-send-email-aik@ozlabs.ru> (raw)
In-Reply-To: <1401886265-6589-1-git-send-email-aik@ozlabs.ru>
This splits one init_proc_970() into a set of small helpers. Later
init_proc_970() will be generalized and will call different set of helpers
depending on the current CPU class.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 97 +++++++++++++++++++++++++++------------------
1 file changed, 58 insertions(+), 39 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 649e893..04497e4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7275,48 +7275,70 @@ static int check_pow_970 (CPUPPCState *env)
return 0;
}
+static void gen_spr_970_hid(CPUPPCState *env)
+{
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ 0x60000000);
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_970_HID5, "HID5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ POWERPC970_HID5_INIT);
+}
+
+static void gen_spr_970_hior(CPUPPCState *env)
+{
+ spr_register(env, SPR_HIOR, "SPR_HIOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_common(CPUPPCState *env)
+{
+ spr_register(env, SPR_CTRL, "SPR_CTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_altivec(CPUPPCState *env)
+{
+ if (!(env->insns_flags & PPC_ALTIVEC)) {
+ return;
+ }
+
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
+}
+
static void init_proc_970 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
- /* Time base */
gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
- /* Memory management */
- /* XXX: not correct */
+ gen_spr_book3s_altivec(env);
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
-
- spr_register(env, SPR_CTRL, "SPR_CTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ gen_spr_book3s_common(env);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 64;
#endif
@@ -7325,9 +7347,6 @@ static void init_proc_970 (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
}
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
--
2.0.0
next prev parent reply other threads:[~2014-06-04 12:51 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-04 12:50 [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 01/30] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 02/30] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` Alexey Kardashevskiy [this message]
2014-06-04 17:27 ` [Qemu-devel] [PATCH v5 03/30] target-ppc: Refactor PPC970 Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 04/30] target-ppc: Make UCTRL a mirror of CTRL Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 05/30] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
2014-06-04 17:27 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 06/30] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 07/30] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 08/30] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 09/30] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 10/30] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 11/30] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 12/30] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
2014-06-04 17:28 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 13/30] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 14/30] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 15/30] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 16/30] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 17/30] target-ppc: Make use of gen_spr_power5p_lpar() " Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 18/30] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 19/30] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 22/30] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
2014-06-04 17:29 ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 25/30] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 26/30] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 29/30] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 30/30] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-06-04 17:30 ` Tom Musta
2014-07-08 14:37 ` Peter Maydell
2014-07-08 14:45 ` Alexander Graf
2014-06-04 17:37 ` [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Tom Musta
2014-06-04 21:51 ` Alexander Graf
2014-06-04 23:37 ` Alexey Kardashevskiy
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