From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 11/33] target-arm: move arm_*_code to a separate file
Date: Thu, 5 Jun 2014 16:22:01 +0200 [thread overview]
Message-ID: <1401978143-11896-12-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com>
These will soon require cpu_ldst.h, so move them out of cpu.h.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-arm/arm_ldst.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 22 ----------------------
target-arm/helper.c | 1 +
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 1 +
5 files changed, 50 insertions(+), 22 deletions(-)
create mode 100644 target-arm/arm_ldst.h
diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
new file mode 100644
index 0000000..007a7d7
--- /dev/null
+++ b/target-arm/arm_ldst.h
@@ -0,0 +1,47 @@
+/*
+ * ARM load/store instructions for code (armeb-user support)
+ *
+ * Copyright (c) 2012 CodeSourcery, LLC
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ARM_LDST_H
+#define ARM_LDST_H
+
+#include "qemu/bswap.h"
+
+/* Load an instruction and return it in the standard little-endian order */
+static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
+ bool do_swap)
+{
+ uint32_t insn = cpu_ldl_code(env, addr);
+ if (do_swap) {
+ return bswap32(insn);
+ }
+ return insn;
+}
+
+/* Ditto, for a halfword (Thumb) instruction */
+static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
+ bool do_swap)
+{
+ uint16_t insn = cpu_lduw_code(env, addr);
+ if (do_swap) {
+ return bswap16(insn);
+ }
+ return insn;
+}
+
+#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 8d04385..7d8332e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1199,26 +1199,4 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
}
}
-/* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
- bool do_swap)
-{
- uint32_t insn = cpu_ldl_code(env, addr);
- if (do_swap) {
- return bswap32(insn);
- }
- return insn;
-}
-
-/* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
- bool do_swap)
-{
- uint16_t insn = cpu_lduw_code(env, addr);
- if (do_swap) {
- return bswap16(insn);
- }
- return insn;
-}
-
#endif
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ec031f5..861baf5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7,6 +7,7 @@
#include "sysemu/sysemu.h"
#include "qemu/bitops.h"
#include "qemu/crc32c.h"
+#include "arm_ldst.h"
#include <zlib.h> /* For crc32 */
#ifndef CONFIG_USER_ONLY
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f964df..a9c4633 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "tcg-op.h"
#include "qemu/log.h"
+#include "arm_ldst.h"
#include "translate.h"
#include "internals.h"
#include "qemu/host-utils.h"
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 7f6fcd6..d499caa 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -30,6 +30,7 @@
#include "tcg-op.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
+#include "arm_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
--
1.8.3.1
next prev parent reply other threads:[~2014-06-05 14:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-05 14:21 [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 01/33] cputlb: Fix regression with TCG interpreter (bug 1310324) Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 02/33] nseries: clean up coding style Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 03/33] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 04/33] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 05/33] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 06/33] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 07/33] softmmu: make do_unaligned_access a method of CPU Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 08/33] softmmu: move ALIGNED_ONLY to cpu.h Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 09/33] softmmu: commonize helper definitions Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 10/33] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
2014-06-05 14:22 ` Paolo Bonzini [this message]
2014-06-05 14:22 ` [Qemu-devel] [PULL 12/33] softmmu: introduce cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 13/33] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 14/33] target-i386: rename KSMAP to KNOSMAP Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 15/33] target-i386: move check_io helpers to seg_helper.c Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 16/33] target-i386: fix kernel accesses with SMAP and CPL = 3 Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 17/33] target-i386: simplify SMAP handling in MMU_KSMAP_IDX Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 18/33] target-i386: fix coding standards in x86_cpu_handle_mmu_fault Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 19/33] target-i386: commonize checks for 2MB and 4KB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 20/33] target-i386: commonize checks for 4MB " Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 21/33] target-i386: commonize checks for PAE and non-PAE Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 22/33] target-i386: tweak handling of PG_NX_MASK Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 23/33] target-i386: introduce do_check_protect label Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 24/33] target-i386: introduce support for 1 GB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 25/33] target-i386: set correct error code for reserved bit access Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 26/33] target-i386: test reserved PS bit on PML4Es Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 27/33] target-i386: raise page fault for reserved physical address bits Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 28/33] target-i386: simplify pte/vaddr calculation Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 29/33] target-i386: unify reserved bits and NX bit check Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 30/33] target-i386: raise page fault for reserved bits in large pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 31/33] target-i386: support long addresses for 4MB pages (PSE-36) Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 32/33] target-i386: fix protection bits in the TLB for SMEP Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 33/33] target-i386: cleanup x86_cpu_get_phys_page_debug Paolo Bonzini
2014-06-05 20:50 ` [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Peter Maydell
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