From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 15/33] target-i386: move check_io helpers to seg_helper.c
Date: Thu, 5 Jun 2014 16:22:05 +0200 [thread overview]
Message-ID: <1401978143-11896-16-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com>
Prepare for adding _kernel accessors there in the next patch.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-i386/misc_helper.c | 42 ------------------------------------------
target-i386/seg_helper.c | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 4f1e30f..4aaf1e4 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -22,48 +22,6 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
-/* check if Port I/O is allowed in TSS */
-static inline void check_io(CPUX86State *env, int addr, int size)
-{
- int io_offset, val, mask;
-
- /* TSS must be a valid 32 bit one */
- if (!(env->tr.flags & DESC_P_MASK) ||
- ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
- env->tr.limit < 103) {
- goto fail;
- }
- io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
- io_offset += (addr >> 3);
- /* Note: the check needs two bytes */
- if ((io_offset + 1) > env->tr.limit) {
- goto fail;
- }
- val = cpu_lduw_kernel(env, env->tr.base + io_offset);
- val >>= (addr & 7);
- mask = (1 << size) - 1;
- /* all bits must be zero to allow the I/O */
- if ((val & mask) != 0) {
- fail:
- raise_exception_err(env, EXCP0D_GPF, 0);
- }
-}
-
-void helper_check_iob(CPUX86State *env, uint32_t t0)
-{
- check_io(env, t0, 1);
-}
-
-void helper_check_iow(CPUX86State *env, uint32_t t0)
-{
- check_io(env, t0, 2);
-}
-
-void helper_check_iol(CPUX86State *env, uint32_t t0)
-{
- check_io(env, t0, 4);
-}
-
void helper_outb(uint32_t port, uint32_t data)
{
cpu_outb(port, data & 0xff);
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index ba47215..31c5508 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -2469,3 +2469,45 @@ void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
}
}
#endif
+
+/* check if Port I/O is allowed in TSS */
+static inline void check_io(CPUX86State *env, int addr, int size)
+{
+ int io_offset, val, mask;
+
+ /* TSS must be a valid 32 bit one */
+ if (!(env->tr.flags & DESC_P_MASK) ||
+ ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
+ env->tr.limit < 103) {
+ goto fail;
+ }
+ io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
+ io_offset += (addr >> 3);
+ /* Note: the check needs two bytes */
+ if ((io_offset + 1) > env->tr.limit) {
+ goto fail;
+ }
+ val = cpu_lduw_kernel(env, env->tr.base + io_offset);
+ val >>= (addr & 7);
+ mask = (1 << size) - 1;
+ /* all bits must be zero to allow the I/O */
+ if ((val & mask) != 0) {
+ fail:
+ raise_exception_err(env, EXCP0D_GPF, 0);
+ }
+}
+
+void helper_check_iob(CPUX86State *env, uint32_t t0)
+{
+ check_io(env, t0, 1);
+}
+
+void helper_check_iow(CPUX86State *env, uint32_t t0)
+{
+ check_io(env, t0, 2);
+}
+
+void helper_check_iol(CPUX86State *env, uint32_t t0)
+{
+ check_io(env, t0, 4);
+}
--
1.8.3.1
next prev parent reply other threads:[~2014-06-05 14:23 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-05 14:21 [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 01/33] cputlb: Fix regression with TCG interpreter (bug 1310324) Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 02/33] nseries: clean up coding style Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 03/33] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 04/33] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 05/33] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 06/33] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 07/33] softmmu: make do_unaligned_access a method of CPU Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 08/33] softmmu: move ALIGNED_ONLY to cpu.h Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 09/33] softmmu: commonize helper definitions Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 10/33] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 11/33] target-arm: move arm_*_code to a separate file Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 12/33] softmmu: introduce cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 13/33] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 14/33] target-i386: rename KSMAP to KNOSMAP Paolo Bonzini
2014-06-05 14:22 ` Paolo Bonzini [this message]
2014-06-05 14:22 ` [Qemu-devel] [PULL 16/33] target-i386: fix kernel accesses with SMAP and CPL = 3 Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 17/33] target-i386: simplify SMAP handling in MMU_KSMAP_IDX Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 18/33] target-i386: fix coding standards in x86_cpu_handle_mmu_fault Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 19/33] target-i386: commonize checks for 2MB and 4KB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 20/33] target-i386: commonize checks for 4MB " Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 21/33] target-i386: commonize checks for PAE and non-PAE Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 22/33] target-i386: tweak handling of PG_NX_MASK Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 23/33] target-i386: introduce do_check_protect label Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 24/33] target-i386: introduce support for 1 GB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 25/33] target-i386: set correct error code for reserved bit access Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 26/33] target-i386: test reserved PS bit on PML4Es Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 27/33] target-i386: raise page fault for reserved physical address bits Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 28/33] target-i386: simplify pte/vaddr calculation Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 29/33] target-i386: unify reserved bits and NX bit check Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 30/33] target-i386: raise page fault for reserved bits in large pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 31/33] target-i386: support long addresses for 4MB pages (PSE-36) Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 32/33] target-i386: fix protection bits in the TLB for SMEP Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 33/33] target-i386: cleanup x86_cpu_get_phys_page_debug Paolo Bonzini
2014-06-05 20:50 ` [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Peter Maydell
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