From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZR-0007WL-Ul for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WsYZH-00009V-TE for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:09 -0400 Received: from mail-wi0-x231.google.com ([2a00:1450:400c:c05::231]:51801) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZH-00009K-LY for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:22:59 -0400 Received: by mail-wi0-f177.google.com with SMTP id f8so3541574wiw.16 for ; Thu, 05 Jun 2014 07:22:58 -0700 (PDT) Received: from playground.station (net-37-117-132-7.cust.vodafonedsl.it. [37.117.132.7]) by mx.google.com with ESMTPSA id p9sm14884136eeg.32.2014.06.05.07.22.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Jun 2014 07:22:58 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Thu, 5 Jun 2014 16:22:12 +0200 Message-Id: <1401978143-11896-23-git-send-email-pbonzini@redhat.com> In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> References: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 22/33] target-i386: tweak handling of PG_NX_MASK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Remove the tail of the PAE case, so that we can use "goto" in the next patch to jump to the protection checks. Signed-off-by: Paolo Bonzini --- target-i386/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index eae3e7e..1460a23 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -657,8 +657,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, ptep &= pte ^ PG_NX_MASK; page_size = 4096; } - - ptep ^= PG_NX_MASK; } else { uint32_t pde; @@ -670,10 +668,11 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, error_code = 0; goto do_fault; } + ptep = pde | PG_NX_MASK; + /* if PSE bit is set, then we use a 4MB page */ if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { page_size = 4096 * 1024; - ptep = pde; pte_addr = pde_addr; pte = pde; } else { @@ -691,11 +690,12 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, goto do_fault; } /* combine pde and pte user and rw protections */ - ptep = pte & pde; + ptep &= pte | PG_NX_MASK; page_size = 4096; } } + ptep ^= PG_NX_MASK; if ((ptep & PG_NX_MASK) && is_write1 == 2) { goto do_fault_protect; } -- 1.8.3.1