From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZY-0007lS-7K for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WsYZP-0000Cn-6z for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:16 -0400 Received: from mail-we0-x231.google.com ([2a00:1450:400c:c03::231]:35211) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZP-0000CT-13 for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:07 -0400 Received: by mail-we0-f177.google.com with SMTP id x48so1180970wes.22 for ; Thu, 05 Jun 2014 07:23:06 -0700 (PDT) Received: from playground.station (net-37-117-132-7.cust.vodafonedsl.it. [37.117.132.7]) by mx.google.com with ESMTPSA id p9sm14884136eeg.32.2014.06.05.07.23.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Jun 2014 07:23:05 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Thu, 5 Jun 2014 16:22:18 +0200 Message-Id: <1401978143-11896-29-git-send-email-pbonzini@redhat.com> In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> References: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 28/33] target-i386: simplify pte/vaddr calculation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org They can moved to after the dirty bit processing, and unified between CR0.PG=1 and CR0.PG=0. Signed-off-by: Paolo Bonzini --- target-i386/helper.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index c52eb5a..153a91b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -527,7 +527,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, hwaddr paddr; uint64_t rsvd_mask = PG_HI_RSVD_MASK; uint32_t page_offset; - target_ulong vaddr, virt_addr; + target_ulong vaddr; is_user = mmu_idx == MMU_USER_IDX; #if defined(DEBUG_MMU) @@ -544,7 +544,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, pte = (uint32_t)pte; } #endif - virt_addr = addr & TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; page_size = 4096; goto do_mapping; @@ -748,9 +747,6 @@ do_check_protect: } stl_phys_notdirty(cs->as, pte_addr, pte); } - /* align to page_size */ - pte &= ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff); - virt_addr = addr & ~(page_size - 1); /* the page can be put in the TLB */ prot = PAGE_READ; @@ -771,11 +767,14 @@ do_check_protect: do_mapping: pte = pte & env->a20_mask; + /* align to page_size */ + pte &= PG_ADDRESS_MASK & ~(page_size - 1); + /* Even if 4MB pages, we map only one 4KB page in the cache to avoid filling it too fast */ - page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1); - paddr = (pte & TARGET_PAGE_MASK) + page_offset; - vaddr = virt_addr + page_offset; + vaddr = addr & TARGET_PAGE_MASK; + page_offset = vaddr & (page_size - 1); + paddr = pte + page_offset; tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return 0; -- 1.8.3.1