From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51839) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZd-0007vG-7B for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WsYZR-0000Da-So for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:21 -0400 Received: from mail-we0-x22d.google.com ([2a00:1450:400c:c03::22d]:39476) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZR-0000DV-F1 for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:09 -0400 Received: by mail-we0-f173.google.com with SMTP id u57so1210974wes.32 for ; Thu, 05 Jun 2014 07:23:08 -0700 (PDT) Received: from playground.station (net-37-117-132-7.cust.vodafonedsl.it. [37.117.132.7]) by mx.google.com with ESMTPSA id p9sm14884136eeg.32.2014.06.05.07.23.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Jun 2014 07:23:08 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Thu, 5 Jun 2014 16:22:20 +0200 Message-Id: <1401978143-11896-31-git-send-email-pbonzini@redhat.com> In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> References: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 30/33] target-i386: raise page fault for reserved bits in large pages List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org In large pages, bit 12 is for PAT, but bits starting at 13 are reserved. Signed-off-by: Paolo Bonzini --- target-i386/cpu.h | 2 ++ target-i386/helper.c | 1 + 2 files changed, 3 insertions(+) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 8ceea8b..51959be 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -249,6 +249,7 @@ #define PG_DIRTY_BIT 6 #define PG_PSE_BIT 7 #define PG_GLOBAL_BIT 8 +#define PG_PSE_PAT_BIT 12 #define PG_NX_BIT 63 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) @@ -260,6 +261,7 @@ #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) #define PG_PSE_MASK (1 << PG_PSE_BIT) #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) +#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) #define PG_ADDRESS_MASK 0x000ffffffffff000LL #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) #define PG_HI_USER_MASK 0x7ff0000000000000LL diff --git a/target-i386/helper.c b/target-i386/helper.c index a2e8bd1..94081e8 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -695,6 +695,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, } do_check_protect: + rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK; if (pte & rsvd_mask) { goto do_fault_rsvd; } -- 1.8.3.1