From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZc-0007uG-9y for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WsYZT-0000ET-91 for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:20 -0400 Received: from mail-wi0-x232.google.com ([2a00:1450:400c:c05::232]:54842) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WsYZT-0000E6-2J for qemu-devel@nongnu.org; Thu, 05 Jun 2014 10:23:11 -0400 Received: by mail-wi0-f178.google.com with SMTP id cc10so3580526wib.17 for ; Thu, 05 Jun 2014 07:23:10 -0700 (PDT) Received: from playground.station (net-37-117-132-7.cust.vodafonedsl.it. [37.117.132.7]) by mx.google.com with ESMTPSA id p9sm14884136eeg.32.2014.06.05.07.23.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Jun 2014 07:23:09 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Thu, 5 Jun 2014 16:22:21 +0200 Message-Id: <1401978143-11896-32-git-send-email-pbonzini@redhat.com> In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> References: <1401978143-11896-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 31/33] target-i386: support long addresses for 4MB pages (PSE-36) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org 4MB pages can use 40-bit addresses by putting the higher 8 bits in bits 20-13 of the PDE. Bit 21 is reserved. Signed-off-by: Paolo Bonzini --- target-i386/cpu.c | 3 +-- target-i386/helper.c | 12 +++++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0f400d4..c8ef936 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -552,8 +552,7 @@ struct X86CPUDefinition { CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) /* partly implemented: - CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) - CPUID_PSE36 (needed for Solaris) */ + CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ /* missing: CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ diff --git a/target-i386/helper.c b/target-i386/helper.c index 94081e8..2b917ad 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -672,8 +672,13 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { page_size = 4096 * 1024; pte_addr = pde_addr; - pte = pde; - goto do_check_protect; + + /* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved. + * Leave bits 20-13 in place for setting accessed/dirty bits below. + */ + pte = pde | ((pde & 0x1fe000) << (32 - 13)); + rsvd_mask = 0x200000; + goto do_check_protect_pse36; } if (!(pde & PG_ACCESSED_MASK)) { @@ -696,6 +701,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, do_check_protect: rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK; +do_check_protect_pse36: if (pte & rsvd_mask) { goto do_fault_rsvd; } @@ -882,7 +888,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) if (!(pde & PG_PRESENT_MASK)) return -1; if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { - pte = pde & ~0x003ff000; /* align to 4MB */ + pte = pde | ((pde & 0x1fe000) << (32 - 13)); page_size = 4096 * 1024; } else { /* page directory entry */ -- 1.8.3.1