From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 08/33] softmmu: move ALIGNED_ONLY to cpu.h
Date: Thu, 5 Jun 2014 16:21:58 +0200 [thread overview]
Message-ID: <1401978143-11896-9-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1401978143-11896-1-git-send-email-pbonzini@redhat.com>
Prepare for moving softmmu_header.h inclusion out of .c files
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-alpha/cpu.h | 1 +
target-alpha/mem_helper.c | 1 -
target-mips/cpu.h | 1 +
target-mips/op_helper.c | 1 -
target-sparc/cpu.h | 2 ++
target-sparc/ldst_helper.c | 1 -
target-xtensa/cpu.h | 1 +
target-xtensa/op_helper.c | 1 -
8 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 07d9f63..d9b861f 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -24,6 +24,7 @@
#include "qemu-common.h"
#define TARGET_LONG_BITS 64
+#define ALIGNED_ONLY
#define CPUArchState struct CPUAlphaState
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index c560bd9..c5c1165 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -134,7 +134,6 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#include "exec/softmmu_exec.h"
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6c2014e..a9b2c7a 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -3,6 +3,7 @@
//#define DEBUG_OP
+#define ALIGNED_ONLY
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_MIPS
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 2b665a1..1c79b68 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2129,7 +2129,6 @@ void helper_wait(CPUMIPSState *env)
#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f72451d..836f87f 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -5,6 +5,8 @@
#include "qemu-common.h"
#include "qemu/bswap.h"
+#define ALIGNED_ONLY
+
#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_DPREGS 16
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 6e04c09..5dec924 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -67,7 +67,6 @@
#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index e210bac..d797d26 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -28,6 +28,7 @@
#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H
+#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index fd514fc..9ce81e2 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -31,7 +31,6 @@
#include "exec/softmmu_exec.h"
#include "exec/address-spaces.h"
-#define ALIGNED_ONLY
#define MMUSUFFIX _mmu
#define SHIFT 0
--
1.8.3.1
next prev parent reply other threads:[~2014-06-05 14:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-05 14:21 [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 01/33] cputlb: Fix regression with TCG interpreter (bug 1310324) Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 02/33] nseries: clean up coding style Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 03/33] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 04/33] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 05/33] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 06/33] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
2014-06-05 14:21 ` [Qemu-devel] [PULL 07/33] softmmu: make do_unaligned_access a method of CPU Paolo Bonzini
2014-06-05 14:21 ` Paolo Bonzini [this message]
2014-06-05 14:21 ` [Qemu-devel] [PULL 09/33] softmmu: commonize helper definitions Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 10/33] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 11/33] target-arm: move arm_*_code to a separate file Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 12/33] softmmu: introduce cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 13/33] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 14/33] target-i386: rename KSMAP to KNOSMAP Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 15/33] target-i386: move check_io helpers to seg_helper.c Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 16/33] target-i386: fix kernel accesses with SMAP and CPL = 3 Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 17/33] target-i386: simplify SMAP handling in MMU_KSMAP_IDX Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 18/33] target-i386: fix coding standards in x86_cpu_handle_mmu_fault Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 19/33] target-i386: commonize checks for 2MB and 4KB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 20/33] target-i386: commonize checks for 4MB " Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 21/33] target-i386: commonize checks for PAE and non-PAE Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 22/33] target-i386: tweak handling of PG_NX_MASK Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 23/33] target-i386: introduce do_check_protect label Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 24/33] target-i386: introduce support for 1 GB pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 25/33] target-i386: set correct error code for reserved bit access Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 26/33] target-i386: test reserved PS bit on PML4Es Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 27/33] target-i386: raise page fault for reserved physical address bits Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 28/33] target-i386: simplify pte/vaddr calculation Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 29/33] target-i386: unify reserved bits and NX bit check Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 30/33] target-i386: raise page fault for reserved bits in large pages Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 31/33] target-i386: support long addresses for 4MB pages (PSE-36) Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 32/33] target-i386: fix protection bits in the TLB for SMEP Paolo Bonzini
2014-06-05 14:22 ` [Qemu-devel] [PULL 33/33] target-i386: cleanup x86_cpu_get_phys_page_debug Paolo Bonzini
2014-06-05 20:50 ` [Qemu-devel] [PULL 00/33] softmmu cleanups and target-i386 paging fixes Peter Maydell
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