From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtNOn-0003GQ-AI for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WtNOm-0001sN-GS for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:33 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48557) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtNOm-0001sC-9P for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:32 -0400 From: Peter Maydell Date: Sat, 7 Jun 2014 21:11:19 +0100 Message-Id: <1402171881-14343-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> References: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/3] target-arm: Add ULL suffix to calculation of page size List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org The maximum block size for AArch64 address translation is 2GB. This means that we need a ULL suffix on our shift to avoid shifting into the sign bit of a signed 32 bit integer. Signed-off-by: Peter Maydell --- target-arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ec031f5..cbad223 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3926,7 +3926,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * These are basically the same thing, although the number * of bits we pull in from the vaddr varies. */ - page_size = (1 << ((granule_sz * (4 - level)) + 3)); + page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor and merge with table attrs */ if (arm_feature(env, ARM_FEATURE_V8)) { -- 1.8.5.4