From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtNOp-0003GX-0f for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WtNOn-0001sq-Bd for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:34 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtNOn-0001sX-5K for qemu-devel@nongnu.org; Sat, 07 Jun 2014 16:39:33 -0400 From: Peter Maydell Date: Sat, 7 Jun 2014 21:11:20 +0100 Message-Id: <1402171881-14343-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> References: <1402171881-14343-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/3] target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org In disas_simd_3same_int(), none of the instructions permit is_q to be false with size == 3 (this would be a vector operation with a one-element vector, and the instruction set encodes those as scalar operations). Replace the always-true ?: check with an assert. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 9f964df..4c9e237 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -8997,7 +8997,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } if (size == 3) { - for (pass = 0; pass < (is_q ? 2 : 1); pass++) { + assert(is_q); + for (pass = 0; pass < 2; pass++) { TCGv_i64 tcg_op1 = tcg_temp_new_i64(); TCGv_i64 tcg_op2 = tcg_temp_new_i64(); TCGv_i64 tcg_res = tcg_temp_new_i64(); -- 1.8.5.4