[Qemu-devel] [PATCH] target-arm: A64: Use PMULL feature bit for PMULL

[Qemu-devel] [PATCH] target-arm: A64: Use PMULL feature bit for PMULL

[Peter Maydell]

Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for
the A64 PMULL, not the AES feature bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Oops, I thought I'd sent this trivial patch already;
it sits between the "finish v8 AArch32 crypto insns" and the
"add v8 AArch64 crypto instructions" patchsets, both already sent.

 linux-user/elfload.c       | 2 +-
 target-arm/translate-a64.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 3241fec..e872493 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -539,7 +539,7 @@ static uint32_t get_elf_hwcap(void)
     /* probe for the extra features */
 #define GET_FEATURE(feat, hwcap) \
     do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
-    GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_PMULL);
+    GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);
 #undef GET_FEATURE
 
     return hwcaps;
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f964df..389a256 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8573,7 +8573,7 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
             return;
         }
         if (size == 3) {
-            if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)) {
+            if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
                 unallocated_encoding(s);
                 return;
             }
-- 
1.9.2