From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu112-00051h-NI for qemu-devel@nongnu.org; Mon, 09 Jun 2014 10:57:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wu111-0005dX-NL for qemu-devel@nongnu.org; Mon, 09 Jun 2014 10:57:40 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu111-0005dP-FX for qemu-devel@nongnu.org; Mon, 09 Jun 2014 10:57:39 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Wu110-00069N-1k for qemu-devel@nongnu.org; Mon, 09 Jun 2014 15:57:38 +0100 From: Peter Maydell Date: Mon, 9 Jun 2014 15:57:18 +0100 Message-Id: <1402325858-23615-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 00/20] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org It always feels a bit odd to write a message to myself here :-) Anyway, here's the latest pile of arm patches... The following changes since commit 4a331bb33bdf112ba95470e5d6ea3561b049c280: Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into staging (2014-06-09 15:00:21 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140609 for you to fetch changes up to ff00c11324276b8064b3a5d00491d0f9c6291a77: target-arm: Delete unused iwmmxt_msadb helper (2014-06-09 15:43:26 +0100) ---------------------------------------------------------------- target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * implement PD0/PD1 bits in TTBCR * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- Ard Biesheuvel (1): target-arm: add support for v8 SHA1 and SHA256 instructions Fabian Aggeler (2): target-arm: Prepare cpreg writefns/readfns for EL3/SecExt target-arm: implement PD0/PD1 bits for TTBCR Grant Likely (1): vexpress: Add support for the -bios flag to provide firmware Ian Campbell (1): target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables Peter Maydell (15): target-arm/cpu64.c: Actually register Cortex-A57 impdef registers target-arm: Allow 3reg_wide undefreq to encode more bad size options target-arm: add support for v8 VMULL.P64 instruction target-arm: A64: Use PMULL feature bit for PMULL target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 target-arm: Remove unnecessary setting of feature bits target-arm: Clean up handling of ARMv8 optional feature bits target-arm: VFPv4 implies half-precision extension target-arm: A64: Implement CRC instructions target-arm: A32/T32: Mask CRC value in calling code, not helper target-arm: A64: Implement AES instructions target-arm: A64: Implement 3-register SHA instructions target-arm: A64: Implement two-register SHA instructions target-arm: Fix errors in writes to generic timer control registers target-arm: Delete unused iwmmxt_msadb helper hw/arm/vexpress.c | 13 +++ linux-user/elfload.c | 9 +- target-arm/cpu.c | 13 +-- target-arm/cpu.h | 19 ++++ target-arm/cpu64.c | 15 ++- target-arm/crypto_helper.c | 257 +++++++++++++++++++++++++++++++++++++++++++-- target-arm/helper-a64.c | 60 +++++------ target-arm/helper-a64.h | 4 +- target-arm/helper.c | 136 +++++++++++++----------- target-arm/helper.h | 14 ++- target-arm/iwmmxt_helper.c | 9 -- target-arm/neon_helper.c | 30 ++++++ target-arm/translate-a64.c | 211 ++++++++++++++++++++++++++++++++++++- target-arm/translate.c | 144 ++++++++++++++++++++++--- 14 files changed, 790 insertions(+), 144 deletions(-)