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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 02/20] target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
Date: Mon,  9 Jun 2014 15:57:20 +0100	[thread overview]
Message-ID: <1402325858-23615-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1402325858-23615-1-git-send-email-peter.maydell@linaro.org>

cpu64.c contains a reginfo list for the impdef registers on
the Cortex-A57; however we forgot to actually call define_arm_cp_regs(),
so it was sitting there doing nothing. Remedy this omission.

Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 8daa622..ff4c2b4 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -128,6 +128,7 @@ static void aarch64_a57_initfn(Object *obj)
     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     cpu->dcz_blocksize = 4; /* 64 bytes */
+    define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
 }
 
 #ifdef CONFIG_USER_ONLY
-- 
1.9.2

  parent reply	other threads:[~2014-06-09 14:57 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-09 14:57 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 01/20] vexpress: Add support for the -bios flag to provide firmware Peter Maydell
2014-06-09 14:57 ` Peter Maydell [this message]
2014-06-09 14:57 ` [Qemu-devel] [PULL 03/20] target-arm: Prepare cpreg writefns/readfns for EL3/SecExt Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 04/20] target-arm: implement PD0/PD1 bits for TTBCR Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 06/20] target-arm: add support for v8 SHA1 and SHA256 instructions Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 12/20] target-arm: Clean up handling of ARMv8 optional " Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 18/20] target-arm: A64: Implement two-register " Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers Peter Maydell
2014-06-09 14:57 ` [Qemu-devel] [PULL 20/20] target-arm: Delete unused iwmmxt_msadb helper Peter Maydell

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