From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1FH-0001kn-Ks for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:12:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wu1FB-0002zt-Dr for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:12:23 -0400 Received: from mail-qg0-x232.google.com ([2607:f8b0:400d:c04::232]:56084) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1FB-0002zV-8x for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:12:17 -0400 Received: by mail-qg0-f50.google.com with SMTP id z60so9061837qgd.9 for ; Mon, 09 Jun 2014 08:12:16 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 10 Jun 2014 01:04:22 +1000 Message-Id: <1402326269-8573-11-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> References: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 5 ++--- target-arm/cpu.h | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 38e5f02..a579ffc 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -478,7 +478,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { + && arm_excp_unmasked(cpu, EXCP_FIQ)) { cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; @@ -493,8 +493,7 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && arm_excp_unmasked(cpu, EXCP_IRQ)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index de00e01..2f262a5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1126,6 +1126,22 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) +{ + CPUARMState *env = cs->env_ptr; + + switch (excp_idx) { + case EXCP_FIQ: + return !(env->daif & PSTATE_F); + case EXCP_IRQ: + return ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->daif & PSTATE_I)); + default: + g_assert_not_reached(); + break; + } +} + static inline CPUARMState *cpu_init(const char *cpu_model) { ARMCPU *cpu = cpu_arm_init(cpu_model); -- 1.8.3.2