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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com,
	aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com,
	john.williams@xilinx.com, greg.bellows@linaro.org,
	pbonzini@redhat.com, alex.bennee@linaro.org,
	christoffer.dall@linaro.org, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms
Date: Tue, 10 Jun 2014 01:04:25 +1000	[thread overview]
Message-ID: <1402326269-8573-14-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>

Avoids the explicit 16bit mask. No functional change.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
 target-arm/internals.h     | 14 +++++++-------
 target-arm/translate-a64.c |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target-arm/internals.h b/target-arm/internals.h
index 08fa697..707643e 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -199,23 +199,23 @@ static inline uint32_t syn_uncategorized(void)
     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
-static inline uint32_t syn_aa64_svc(uint32_t imm16)
+static inline uint32_t syn_aa64_svc(uint16_t imm16)
 {
-    return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
+    return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16;
 }
 
-static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
+static inline uint32_t syn_aa32_svc(uint16_t imm16, bool is_thumb)
 {
-    return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
+    return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | imm16
         | (is_thumb ? 0 : ARM_EL_IL);
 }
 
-static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
+static inline uint32_t syn_aa64_bkpt(uint16_t imm16)
 {
-    return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
+    return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16;
 }
 
-static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
+static inline uint32_t syn_aa32_bkpt(uint16_t imm16, bool is_thumb)
 {
     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
         | (is_thumb ? 0 : ARM_EL_IL);
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a9c4633..3589898 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1433,7 +1433,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
 {
     int opc = extract32(insn, 21, 3);
     int op2_ll = extract32(insn, 0, 5);
-    int imm16 = extract32(insn, 5, 16);
+    uint16_t imm16 = extract32(insn, 5, 16);
 
     switch (opc) {
     case 0:
-- 
1.8.3.2

  parent reply	other threads:[~2014-06-09 15:14 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-09 15:04 [Qemu-devel] [PATCH v2 00/17] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 01/17] target-arm: A64: Break out aarch64_save/restore_sp Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 02/17] target-arm: A64: Respect SPSEL in ERET SP restore Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 03/17] target-arm: A64: Respect SPSEL when taking exceptions Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 04/17] target-arm: Make far_el1 an array Edgar E. Iglesias
2014-06-11 15:11   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 05/17] target-arm: Add ESR_EL2 and 3 Edgar E. Iglesias
2014-06-11 15:13   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 06/17] target-arm: Add FAR_EL2 " Edgar E. Iglesias
2014-06-11 15:15   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 07/17] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-06-11 15:48   ` Greg Bellows
2014-06-11 15:58     ` Greg Bellows
2014-06-16  6:36     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-06-10 22:06   ` Aggeler  Fabian
2014-06-11  1:19     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 09/17] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-06-11 16:51   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func Edgar E. Iglesias
2014-06-11 17:16   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 11/17] target-arm: Don't take interrupts targeting lower ELs Edgar E. Iglesias
2014-06-11 17:17   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-06-11 18:36   ` Greg Bellows
2014-06-09 15:04 ` Edgar E. Iglesias [this message]
2014-06-11 19:19   ` [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms Greg Bellows
2014-06-11 21:05     ` Peter Maydell
2014-06-11 21:19       ` Greg Bellows
2014-06-16 23:13       ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 14/17] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-06-11 20:14   ` Greg Bellows
2014-06-16 23:28     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 15/17] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-06-11 21:14   ` Greg Bellows
2014-06-16  6:03     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 16/17] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-06-11 22:08   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 17/17] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-06-11 22:31   ` Greg Bellows

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