From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1HQ-00058g-Iy for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:14:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wu1HB-0003fp-PA for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:14:36 -0400 Received: from mail-qa0-x232.google.com ([2607:f8b0:400d:c00::232]:33316) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wu1HB-0003fl-L6 for qemu-devel@nongnu.org; Mon, 09 Jun 2014 11:14:21 -0400 Received: by mail-qa0-f50.google.com with SMTP id j15so7826491qaq.23 for ; Mon, 09 Jun 2014 08:14:21 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 10 Jun 2014 01:04:25 +1000 Message-Id: <1402326269-8573-14-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> References: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Avoids the explicit 16bit mask. No functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/internals.h | 14 +++++++------- target-arm/translate-a64.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target-arm/internals.h b/target-arm/internals.h index 08fa697..707643e 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -199,23 +199,23 @@ static inline uint32_t syn_uncategorized(void) return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; } -static inline uint32_t syn_aa64_svc(uint32_t imm16) +static inline uint32_t syn_aa64_svc(uint16_t imm16) { - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16; } -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb) +static inline uint32_t syn_aa32_svc(uint16_t imm16, bool is_thumb) { - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | imm16 | (is_thumb ? 0 : ARM_EL_IL); } -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +static inline uint32_t syn_aa64_bkpt(uint16_t imm16) { - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16; } -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb) +static inline uint32_t syn_aa32_bkpt(uint16_t imm16, bool is_thumb) { return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | (is_thumb ? 0 : ARM_EL_IL); diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index a9c4633..3589898 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1433,7 +1433,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) { int opc = extract32(insn, 21, 3); int op2_ll = extract32(insn, 0, 5); - int imm16 = extract32(insn, 5, 16); + uint16_t imm16 = extract32(insn, 5, 16); switch (opc) { case 0: -- 1.8.3.2