From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtE-0007YZ-NO for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVt6-0004CO-Hp for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:40 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:2310) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt6-0004C9-CE for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:32 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:54:54 +0200 Message-ID: <1402444514-19658-13-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Signed-off-by: Fabian Aggeler --- target-arm/helper.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8333b52..b9b458e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3429,14 +3429,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = 1; + unsigned int target_mode; bool route_to_el2 = false; - /* FIXME: Use actual secure state. */ - bool secure = false; - if (!env->aarch64) { - /* TODO: Add EL2 and 3 exception handling for AArch32. */ - return 1; - } + bool secure = arm_is_secure(env); if (!secure && arm_feature(env, ARM_FEATURE_EL2) @@ -3458,18 +3454,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) } break; case EXCP_FIQ: - case EXCP_IRQ: { - const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; - const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; - - if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { - target_el = 2; - } - if (env->cp15.scr_el3 & scr_mask) { - target_el = 3; - } - break; - } + case EXCP_IRQ: + target_el = arm_phys_excp_target_el(cs, &target_mode, excp_idx, + cur_el, secure); + break; case EXCP_VIRQ: case EXCP_VFIQ: target_el = 1; -- 1.8.3.2