From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtE-0007YA-59 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVt7-0004Cp-2g for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:40 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14827) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt6-0004CS-Te for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:33 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:54:55 +0200 Message-ID: <1402444514-19658-14-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index b9b458e..2fbecfa 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3705,12 +3705,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: -- 1.8.3.2