From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtK-0007jl-KT for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVtC-0004G7-RV for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:46 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14839) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtC-0004FR-8v for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:38 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:55:04 +0200 Message-ID: <1402444514-19658-23-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Rename CSSELR (cache size selection register) and add secure instance (Aarch32). Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 9 +++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 908ff60..6d3deb1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t csselr_ns; + uint64_t csselr_s; + }; + struct { + uint64_t csselr_el1; + }; + }; union { /* System control register. */ struct { uint64_t sctlr_ns; diff --git a/target-arm/helper.c b/target-arm/helper.c index 5655bd8..69d9612 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -700,7 +700,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + return cpu->ccsidr[A32_BANKED_REG_GET(env, csselr)]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -808,10 +808,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, - { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, + { .name = "CSSELR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_el1) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ -- 1.8.3.2