From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtC-0007X9-Te for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVt1-00049m-DD for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:38 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14808) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt1-000499-19 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:27 -0400 From: Fabian Aggeler Date: Wed, 11 Jun 2014 01:54:45 +0200 Message-ID: <1402444514-19658-4-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 4 ++-- target-arm/machine.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 060664f..903aa01 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -153,8 +153,8 @@ typedef struct CPUARMState { /* Banked registers. */ uint64_t banked_spsr[8]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint32_t banked_r13[8]; + uint32_t banked_r14[8]; /* These hold r8-r12. */ uint32_t usr_regs[5]; diff --git a/target-arm/machine.c b/target-arm/machine.c index 3bcc7cc..5ed495e 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -234,8 +234,8 @@ const VMStateDescription vmstate_arm_cpu = { }, VMSTATE_UINT32(env.spsr, ARMCPU), VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), -- 1.8.3.2