From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwZO0-0003n8-2Q for qemu-devel@nongnu.org; Mon, 16 Jun 2014 12:04:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WwZNr-0003bA-1W for qemu-devel@nongnu.org; Mon, 16 Jun 2014 12:03:56 -0400 From: Tom Musta Date: Mon, 16 Jun 2014 11:03:19 -0500 Message-Id: <1402934602-29002-2-git-send-email-tommusta@gmail.com> In-Reply-To: <1402934602-29002-1-git-send-email-tommusta@gmail.com> References: <1402934602-29002-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 1/4] linux-user: Correct AUXV Cache Line Sizes for PowerPC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: tommusta@gmail.com, qemu-ppc@nongnu.org Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the CPU model's cache line sizes. This fixes memory clobbering problems on more recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction when N is sufficiently large and many of the newer server CPUs have cache lines sizes of 128 bytes. Signed-off-by: Tom Musta --- linux-user/elfload.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 127c565..9a32899 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -767,8 +767,9 @@ static uint32_t get_elf_hwcap(void) #define DLINFO_ARCH_ITEMS 5 #define ARCH_DLINFO \ do { \ - NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \ - NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \ + PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \ + NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \ + NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \ NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \ /* \ * Now handle glibc compatibility. \ -- 1.7.1