From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxJz3-000195-AL for qemu-devel@nongnu.org; Wed, 18 Jun 2014 13:49:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxJz2-0001PC-4N for qemu-devel@nongnu.org; Wed, 18 Jun 2014 13:49:17 -0400 Received: from qemu.weilnetz.de ([2a03:4000:2:362::1]:47164) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxJz1-0001Oe-Ox for qemu-devel@nongnu.org; Wed, 18 Jun 2014 13:49:16 -0400 From: Stefan Weil Date: Wed, 18 Jun 2014 19:49:11 +0200 Message-Id: <1403113751-19799-1-git-send-email-sw@weilnetz.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] libvixl: Fix wrong format strings List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Stefan Weil , Richard Henderson When the compiler is told to check the arguments of AppendToOutput, it reports several errors of this kind: error: format =E2=80=98%d=E2=80=99 expects argument of type =E2=80=98int=E2= =80=99, but argument 3 has type =E2=80=98int64_t {aka long int}=E2=80=99 [-Werro= r=3Dformat] Fix those bugs by using the correct format strings with PRId64, PRIx64. Signed-off-by: Stefan Weil --- Hello Peter, if you want to fix the format strings before upstream updates the code, you can use this patch. It fails with checkpatch.pl, but that's normal in this case. Regards Stefan disas/libvixl/a64/disasm-a64.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/disas/libvixl/a64/disasm-a64.cc b/disas/libvixl/a64/disasm-a= 64.cc index aa133a9..f81ce4b 100644 --- a/disas/libvixl/a64/disasm-a64.cc +++ b/disas/libvixl/a64/disasm-a64.cc @@ -1369,7 +1369,7 @@ int Disassembler::SubstituteImmediateField(Instruct= ion* instr, VIXL_ASSERT(format[5] =3D=3D 'L'); AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide()); if (instr->ShiftMoveWide() > 0) { - AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide()); + AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide())= ; } } return 8; @@ -1418,7 +1418,7 @@ int Disassembler::SubstituteImmediateField(Instruct= ion* instr, } case 'F': { // IFPSingle, IFPDouble or IFPFBits. if (format[3] =3D=3D 'F') { // IFPFbits. - AppendToOutput("#%d", 64 - instr->FPScale()); + AppendToOutput("#%" PRId64, 64 - instr->FPScale()); return 8; } else { AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(), @@ -1439,23 +1439,23 @@ int Disassembler::SubstituteImmediateField(Instru= ction* instr, return 5; } case 'P': { // IP - Conditional compare. - AppendToOutput("#%d", instr->ImmCondCmp()); + AppendToOutput("#%" PRId64, instr->ImmCondCmp()); return 2; } case 'B': { // Bitfields. return SubstituteBitfieldImmediateField(instr, format); } case 'E': { // IExtract. - AppendToOutput("#%d", instr->ImmS()); + AppendToOutput("#%" PRId64, instr->ImmS()); return 8; } case 'S': { // IS - Test and branch bit. - AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) | - instr->ImmTestBranchBit40()); + AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) | + instr->ImmTestBranchBit40()); return 2; } case 'D': { // IDebug - HLT and BRK instructions. - AppendToOutput("#0x%x", instr->ImmException()); + AppendToOutput("#0x%" PRIx64, instr->ImmException()); return 6; } default: { @@ -1626,12 +1626,12 @@ int Disassembler::SubstituteExtendField(Instructi= on* instr, (((instr->ExtendMode() =3D=3D UXTW) && (instr->SixtyFourBits() =3D= =3D 0)) || (instr->ExtendMode() =3D=3D UXTX))) { if (instr->ImmExtendShift() > 0) { - AppendToOutput(", lsl #%d", instr->ImmExtendShift()); + AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift()); } } else { AppendToOutput(", %s", extend_mode[instr->ExtendMode()]); if (instr->ImmExtendShift() > 0) { - AppendToOutput(" #%d", instr->ImmExtendShift()); + AppendToOutput(" #%" PRId64, instr->ImmExtendShift()); } } return 3; @@ -1660,7 +1660,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instru= ction* instr, if (!((ext =3D=3D UXTX) && (shift =3D=3D 0))) { AppendToOutput(", %s", extend_mode[ext]); if (shift !=3D 0) { - AppendToOutput(" #%d", instr->SizeLS()); + AppendToOutput(" #%" PRId64, instr->SizeLS()); } } return 9; --=20 1.7.10.4