From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxdNJ-0003LN-S4 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:31:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxdND-0007LI-MW for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:31:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:11454) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxdND-0007LD-FB for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:31:31 -0400 Message-ID: <1403188286.2163.4.camel@localhost.localdomain> From: Marcel Apfelbaum Date: Thu, 19 Jun 2014 17:31:26 +0300 In-Reply-To: <20140619142142.GC4544@redhat.com> References: <1403185937-19515-1-git-send-email-marcel.a@redhat.com> <20140619142142.GC4544@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] hw/pci: reserve IO and mem for pci express downstream ports with no devices attached List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: kevin@koconnor.net, seabios@seabios.org, qemu-devel@nongnu.org On Thu, 2014-06-19 at 17:21 +0300, Michael S. Tsirkin wrote: > On Thu, Jun 19, 2014 at 04:52:17PM +0300, Marcel Apfelbaum wrote: > > commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830 > > hw/pci: reserve IO and mem for pci-2-pci bridges with no devices = attached > >=20 > > introduced support for hot-plugging devices behind pci-2-pci bridges. > > Extend hotplug support also for pci express downstream ports. > >=20 > > Signed-off-by: Marcel Apfelbaum > > --- > > src/fw/pciinit.c | 23 +++++++++++++++++++++-- > > src/hw/pci_regs.h | 2 ++ > > 2 files changed, 23 insertions(+), 2 deletions(-) > >=20 > > diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c > > index 0ad548f..edb3fe9 100644 > > --- a/src/fw/pciinit.c > > +++ b/src/fw/pciinit.c > > @@ -636,6 +636,25 @@ pci_region_create_entry(struct pci_bus *bus, str= uct pci_device *dev, > > return entry; > > } > > =20 > > +static int pci_bus_hotplug_support(struct pci_bus *bus) > > +{ > > + u8 shpc_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHP= C); > > + u8 pcie_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_EXP= ); > > + int downstream_port =3D 0; > > + int slot_implemented =3D 0; > > + > > + if (pcie_cap) { > > + u16 pcie_flags =3D pci_config_readw(bus->bus_dev->bdf, > > + pcie_cap + PCI_EXP_FLAGS); > > + u16 port_type =3D ((pcie_flags & PCI_EXP_FLAGS_TYPE) >> > > + PCI_EXP_FLAGS_TYPE_SHIFT) & 0xf; >=20 > 0xf is not needed here: PCI_EXP_FLAGS_TYPE is enough. > Also should be u8. OK, thanks >=20 > > + downstream_port =3D (port_type =3D=3D PCI_EXP_TYPE_DOWNSTREA= M) || > > + (port_type =3D=3D PCI_EXP_TYPE_ROOT_PORT); >=20 > This is correct, the spec says: > Configuration Space, and other capabilities. > 8 Slot Implemented =E2=80=93 When Set, this bit indicates that the = Link > HwInit associated with this Port is connected to a slot (as compare= d to > being connected to a system-integrated device or being > disabled). > This bit is valid for Downstream Ports. This bit is undefined for > Upstream Ports. >=20 > Maybe add a comment in case people will wonder. Sure >=20 > > + slot_implemented =3D !!(pcie_flags & PCI_EXP_FLAGS_SLOT); >=20 > I would do > return downstream_port && slot_implemented; > here, avoid testing shpc for express devices. >=20 > Also allows moving downstream_port && slot_implemented here. Makes sense >=20 > > + } > > + return shpc_cap || (downstream_port && slot_implemented); > > +} > > + > > static int pci_bios_check_devices(struct pci_bus *busses) > > { > > dprintf(1, "PCI: check devices\n"); > > @@ -678,7 +697,7 @@ static int pci_bios_check_devices(struct pci_bus = *busses) > > continue; > > struct pci_bus *parent =3D &busses[pci_bdf_to_bus(s->bus_dev= ->bdf)]; > > int type; > > - u8 shpc_cap =3D pci_find_capability(s->bus_dev, PCI_CAP_ID_S= HPC); > > + int hotplug_support =3D pci_bus_hotplug_support(s); > > for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { > > u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? > > PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; > > @@ -687,7 +706,7 @@ static int pci_bios_check_devices(struct pci_bus = *busses) > > if (pci_region_align(&s->r[type]) > align) > > align =3D pci_region_align(&s->r[type]); > > u64 sum =3D pci_region_sum(&s->r[type]); > > - if (!sum && shpc_cap) > > + if (!sum && hotplug_support) > > sum =3D align; /* reserve min size for hot-plug */ > > u64 size =3D ALIGN(sum, align); > > int is64 =3D pci_bios_bridge_region_is64(&s->r[type], > > diff --git a/src/hw/pci_regs.h b/src/hw/pci_regs.h > > index e5effd4..6a71569 100644 > > --- a/src/hw/pci_regs.h > > +++ b/src/hw/pci_regs.h > > @@ -426,6 +426,8 @@ > > #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ > > #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ > > =20 > > +#define PCI_EXP_FLAGS_TYPE_SHIFT 4 > > + >=20 > It's generally not a good idea to randomly add macros > in random places. > In this case this is not needed. Just call __ffs on > PCI_EXP_FLAGS_TYPE. I didn't see any usage of __ffs method on seabios code, so I wondered if adding an include to string.h would be ok. Would it? Thanks, Marcel >=20 > > /* Extended Capabilities (PCI-X 2.0 and Express) */ > > #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) > > #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) > > --=20 > > 1.8.3.1