From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxdcE-0003PR-TF for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:47:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wxdc8-0004tP-PU for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:47:02 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:3089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxdc8-0004tK-HI for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:46:56 -0400 From: Leon Alrae Date: Thu, 19 Jun 2014 15:45:42 +0100 Message-ID: <1403189143-54609-12-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com> References: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 561eeb0..1f199fd 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -357,8 +357,10 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | + (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (3 << CP0C4_IE) | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | @@ -370,6 +372,9 @@ static const mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP0_PageGrain = (1 << CP0PG_XIE) | (1 << CP0PG_RIE) | (1 << CP0PG_IEC), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_XIE) | (1 << CP0PG_RIE) | + (1 << CP0PG_IEC), .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), -- 1.7.5.4