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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com,
	leon.alrae@imgtec.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers
Date: Thu, 19 Jun 2014 15:45:33 +0100	[thread overview]
Message-ID: <1403189143-54609-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com>


Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/machine.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/target-mips/machine.c b/target-mips/machine.c
index 0496faa..966c5ef 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -144,6 +144,9 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_sbe32s(f, &env->CP0_DataHi);
     qemu_put_betls(f, &env->CP0_ErrorEPC);
     qemu_put_sbe32s(f, &env->CP0_DESAVE);
+    for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
+        qemu_put_betls(f, &env->CP0_KScratch[i]);
+    }
 
     /* Save inactive TC state */
     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
@@ -301,6 +304,11 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_sbe32s(f, &env->CP0_DataHi);
     qemu_get_betls(f, &env->CP0_ErrorEPC);
     qemu_get_sbe32s(f, &env->CP0_DESAVE);
+    if (version_id >= 4) {
+        for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
+            qemu_get_betls(f, &env->CP0_KScratch[i]);
+        }
+    }
 
     /* Load inactive TC state */
     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) {
-- 
1.7.5.4

  parent reply	other threads:[~2014-06-19 14:46 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-19 14:45 [Qemu-devel] [PATCH 00/12] implement features required in MIPS64 Release 6 Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 01/12] target-mips: add KScratch registers Leon Alrae
2014-06-20 22:02   ` Aurelien Jarno
2014-07-08  8:18     ` Leon Alrae
2014-06-19 14:45 ` Leon Alrae [this message]
2014-06-19 17:43   ` [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support " Richard Henderson
2014-07-08  8:31     ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-06-19 22:13   ` Aurelien Jarno
2014-07-08  8:07     ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception Leon Alrae
2014-06-19 22:13   ` Aurelien Jarno
2014-06-19 14:45 ` [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core Leon Alrae

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