From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60454) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxdc1-000306-9o for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:46:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wxdbv-0004Z8-6g for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:46:49 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:24642) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxdbv-0004YZ-1C for qemu-devel@nongnu.org; Thu, 19 Jun 2014 10:46:43 -0400 From: Leon Alrae Date: Thu, 19 Jun 2014 15:45:34 +0100 Message-ID: <1403189143-54609-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com> References: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Signed-off-by: Leon Alrae --- target-mips/helper.c | 27 ++++++++++++++++----------- 1 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target-mips/helper.c b/target-mips/helper.c index 064622c..b59ac13 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -26,6 +26,12 @@ #include "cpu.h" enum { + MIPS_DATA_LOAD = 0, + MIPS_DATA_STORE = 1, + MIPS_INST_FETCH = 2 +}; + +enum { TLBRET_DIRTY = -4, TLBRET_INVALID = -3, TLBRET_NOMATCH = -2, @@ -86,7 +92,7 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, /* Check access rights */ if (!(n ? tlb->V1 : tlb->V0)) return TLBRET_INVALID; - if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { + if (rw != MIPS_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical = tlb->PFN[n] | (address & (mask >> 1)); *prot = PAGE_READ; if (n ? tlb->D1 : tlb->D0) @@ -212,25 +218,28 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, case TLBRET_BADADDR: /* Reference to kernel address from user mode or supervisor mode */ /* Reference to supervisor address from user mode */ - if (rw) + if (rw == MIPS_DATA_STORE) { exception = EXCP_AdES; - else + } else { exception = EXCP_AdEL; + } break; case TLBRET_NOMATCH: /* No TLB match for a mapped address */ - if (rw) + if (rw == MIPS_DATA_STORE) { exception = EXCP_TLBS; - else + } else { exception = EXCP_TLBL; + } error_code = 1; break; case TLBRET_INVALID: /* TLB match with no valid bit */ - if (rw) + if (rw == MIPS_DATA_STORE) { exception = EXCP_TLBS; - else + } else { exception = EXCP_TLBL; + } break; case TLBRET_DIRTY: /* TLB match but 'D' bit is cleared */ @@ -287,8 +296,6 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); - rw &= 1; - /* data access */ #if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() @@ -322,8 +329,6 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r int access_type; int ret = 0; - rw &= 1; - /* data access */ access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, -- 1.7.5.4