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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/14] target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()
Date: Thu, 19 Jun 2014 18:36:48 +0100	[thread overview]
Message-ID: <1403199417-8833-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1403199417-8833-1-git-send-email-peter.maydell@linaro.org>

In handle_simd_shift_fpint_conv(), the combination of is_double == true,
is_scalar == false and is_q == false is an unallocated encoding; the
'both parts false' case of the nested ?: expression for calculating
maxpass is therefore unreachable and can be removed.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1402171881-14343-4-git-send-email-peter.maydell@linaro.org
---
 target-arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cbc8a35..33b5025 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6539,7 +6539,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
     tcg_shift = tcg_const_i32(fracbits);
 
     if (is_double) {
-        int maxpass = is_scalar ? 1 : is_q ? 2 : 1;
+        int maxpass = is_scalar ? 1 : 2;
 
         for (pass = 0; pass < maxpass; pass++) {
             TCGv_i64 tcg_op = tcg_temp_new_i64();
-- 
1.9.2

  parent reply	other threads:[~2014-06-19 17:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-19 17:36 [Qemu-devel] [PULL 00/14] target-arm queue Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 01/14] target-arm: implement PD0/PD1 bits for TTBCR Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 02/14] hw/arm/spitz: Avoid clash with Windows header symbol MOD_SHIFT Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 03/14] target-arm: Add ULL suffix to calculation of page size Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 04/14] target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() Peter Maydell
2014-06-19 17:36 ` Peter Maydell [this message]
2014-06-19 17:36 ` [Qemu-devel] [PULL 06/14] hw/arm/vexpress: Forbid specifying flash contents in two ways at once Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 07/14] hw/block/pflash_cfi01: Report correct size info for parallel configs Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 08/14] kvm: Handle exit reason KVM_EXIT_SYSTEM_EVENT Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 09/14] target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 10/14] target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 11/14] target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64 Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 12/14] target-arm: Introduce per-CPU field for PSCI version Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 13/14] Use PSCI v0.2 compatible string when KVM or TCG provides it Peter Maydell
2014-06-19 17:36 ` [Qemu-devel] [PULL 14/14] armv7m_nvic: fix AIRCR implementation Peter Maydell
2014-06-20 17:00 ` [Qemu-devel] [PULL 00/14] target-arm queue Peter Maydell

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