From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxzae-00063o-Fh for qemu-devel@nongnu.org; Fri, 20 Jun 2014 10:14:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxzaY-0007Ab-CQ for qemu-devel@nongnu.org; Fri, 20 Jun 2014 10:14:52 -0400 Received: from mail-qa0-x230.google.com ([2607:f8b0:400d:c00::230]:54776) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxzaY-0007AL-7j for qemu-devel@nongnu.org; Fri, 20 Jun 2014 10:14:46 -0400 Received: by mail-qa0-f48.google.com with SMTP id x12so3197058qac.7 for ; Fri, 20 Jun 2014 07:14:45 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 20 Jun 2014 07:13:35 -0700 Message-Id: <1403273621-2584-20-git-send-email-rth@twiddle.net> In-Reply-To: <1403273621-2584-1-git-send-email-rth@twiddle.net> References: <1403273621-2584-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 19/25] tcg-ppc64: Support mulsh_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: tommusta@gmail.com, av1474@comtv.ru Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 5 +++++ tcg/ppc64/tcg-target.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a5ad140..02ee8e2 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -410,6 +410,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define OR XO31(444) #define XOR XO31(316) #define MULLW XO31(235) +#define MULHW XO31( 75) #define MULHWU XO31( 11) #define DIVW XO31(491) #define DIVWU XO31(459) @@ -2263,6 +2264,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_muluh_i32: tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); break; + case INDEX_op_mulsh_i32: + tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + break; case INDEX_op_muluh_i64: tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); break; @@ -2329,6 +2333,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_muluh_i32, { "r", "r", "r" } }, + { INDEX_op_mulsh_i32, { "r", "r", "r" } }, #if TCG_TARGET_REG_BITS == 64 { INDEX_op_ld8u_i64, { "r", "r" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 7b90087..066e74b 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -71,7 +71,7 @@ typedef enum { #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 -#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 -- 1.9.3