From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wyuzz-0003s5-38 for qemu-devel@nongnu.org; Sun, 22 Jun 2014 23:32:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wyuzt-0001ov-0Q for qemu-devel@nongnu.org; Sun, 22 Jun 2014 23:32:51 -0400 Received: from gate.crashing.org ([63.228.1.57]:58372) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wyuzs-0001ok-Nu for qemu-devel@nongnu.org; Sun, 22 Jun 2014 23:32:44 -0400 Message-ID: <1403494347.4587.122.camel@pasglop> From: Benjamin Herrenschmidt Date: Mon, 23 Jun 2014 13:32:27 +1000 In-Reply-To: <1403484330.4587.118.camel@pasglop> References: <1402914604.7661.46.camel@pasglop> <1403484330.4587.118.camel@pasglop> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Endian control register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: bochs-developers@lists.sourceforge.net Cc: "qemu-devel@nongnu.org" On Mon, 2014-06-23 at 10:45 +1000, Benjamin Herrenschmidt wrote: > > Another option would be to use an unused bit if the ENABLE register > and simply force it to 1 on reads when the endian control register > is present... though in this case it might be a better idea to use > that bit to indicate the presence of "extended flags", use a new > register 0xb as "EXTENDED_FLAGS", and use a flag in there as indicative > of the presence of endian control which becomes register 0xc. > > That way you also have room for more extensions if you wish to do > so in the future. I just remembered... we use 16-bit wide ports, we could just use the top 8 bits of the enable register as "capabilities" ... Cheers, Ben.